公开(公告)号：WO2003021409A2

公开(公告)日：2003-03-13

申请号：PCT/US2002/027666

申请日：2002-08-29

Applicant: ANALOG DEVICES, INC.

Inventor： BIRK, Palle ,  SOERENSEN, Joern ,  ALLEN, Michael

IPC: G06F1/32

CPC classification number: G06F11/3636 ,  G06F1/04 ,  G06F1/08 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3869 ,  G06F9/4843 ,  G06F12/0842 ,  G06F12/0859 ,  G06F13/28 ,  G06F13/385 ,  G06F2213/3814 ,  H03L7/0802 ,  H03L7/095 ,  H03L7/183 ,  H04W88/06 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/151 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D10/24 ,  Y02D50/20 ,  Y02D70/1222 ,  Y02D70/124 ,  Y02D70/142 ,  Y02D70/144 ,  Y02D70/164 ,  Y10S331/02

Abstract: A dynamic power controller is provided that identifies a clock frequency requirement of a processor and determines a voltage requirement to support the clock frequency requirement. The dynamic power controller transitions the processor to a power state defined by the clock frequency requirement and the voltage requirement. In particular, a voltage level indicated by the voltage requirement is supplied to the processor and the frequency distribution indicated by the frequency requirement is provided to the clocks signals of the processor.

Abstract translation: 提供动态功率控制器，其识别处理器的时钟频率要求并确定电压要求以支持时钟频率要求。 动态功率控制器将处理器转换到由时钟频率要求和电压要求所定义的功率状态。 具体地说，将由电压要求表示的电压电平提供给处理器，并将由频率要求表示的频率分布提供给处理器的时钟信号。

公开(公告)号：WO2003021600A3

公开(公告)日：2003-03-13

申请号：PCT/US2002/027684

申请日：2002-08-29

Applicant: ANALOG DEVICES, INC.

Inventor： SOERENSEN, Joern ,  KRIVACEK, Paul, D. ,  ALLEN, Michael ,  BANSE, Mark

IPC: G11C7/00

Abstract: Methods and apparatus for accessing flash memory in a continued burst mode are provided. The apparatus includes a processor for executing instructions including memory access instructions, the processor generating a next access signal that indicates if a next memory access is in sequence with a current memory access, a memory having a continued burst mode of operation, and a bus interface for controlling access to the memory in response to the memory access instructions. The bus interface unit enables the continued burst mode of the memory while the next access signal is asserted.

公开(公告)号：WO2004023288A2

公开(公告)日：2004-03-18

申请号：PCT/US2003/027743

申请日：2003-09-05

Applicant: INTEL CORPORATION ,  ANALOG DEVICES, INC.

Inventor： SINGH, Ravi, P. ,  TOMAZIN, Thomas ,  ROTH, Charles, P. ,  FRIDMAN, Jose ,  ALLEN, Michael

IPC: G06F9/00

CPC classification number: G06F9/4812

Abstract: A processor may support a self-nesting mode in which an interrupt may preempt another interrupt of the same priority level. The execution of an interrupt service routine (ISR) for an interrupt may be deferred until the ISR for a subsequently received interrupt of the same priority level is completed.

Abstract translation: 处理器可以支持自嵌套模式，其中中断可以抢占相同优先级的另一个中断。 执行中断服务程序（ISR）可能会延迟，直到完成相同优先级的后续接收到的中断的ISR为止。

公开(公告)号：WO2003021800A1

公开(公告)日：2003-03-13

申请号：PCT/US2002/027462

申请日：2002-08-29

Applicant: ANALOG DEVICES, INC.

Inventor： SOERENSEN, Joern ,  ALLEN, Michael ,  ANAND, Hitesh

IPC: H04B1/16

CPC classification number: G06F11/3636 ,  G06F1/04 ,  G06F1/08 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3869 ,  G06F9/4843 ,  G06F12/0842 ,  G06F12/0859 ,  G06F13/28 ,  G06F13/385 ,  G06F2213/3814 ,  H03L7/0802 ,  H03L7/095 ,  H03L7/183 ,  H04W88/06 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/151 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D10/24 ,  Y02D50/20 ,  Y02D70/1222 ,  Y02D70/124 ,  Y02D70/142 ,  Y02D70/144 ,  Y02D70/164 ,  Y10S331/02

Abstract: A digital baseband processor is provided which receives a system clock generated by a system oscillator and generates a plurality of clock signals from the system clock. The digital baseband processor includes a digital signal processor for executing digital signal processor instructions, a microcontroller for executing microcontroller instructions, and other modules which may require one of the plurality of clock signals for operation. The digital baseband processor also includes a power management circuit which may power down the system oscillator when modules such as the digital signal processor and microcontroller do not require clock signals derived from the system oscillator. The power management circuit may gate off clock signals to modules when those modules do not require clock signals, without powering down the system oscillator.

Abstract translation: 提供了一种数字基带处理器，其接收由系统振荡器产生的系统时钟，并从系统时钟产生多个时钟信号。 数字基带处理器包括用于执行数字信号处理器指令的数字信号处理器，用于执行微控制器指令的微控制器以及可能需要多个时钟信号中的一个用于操作的其它模块。 数字基带处理器还包括一个电源管理电路，当诸如数字信号处理器和微控制器的模块不需要从系统振荡器导出的时钟信号时，该电源管理电路可能会关闭系统振荡器。 当这些模块不需要时钟信号而不关闭系统振荡器时，电源管理电路可以关闭时钟信号到模块。

公开(公告)号：WO2003021600A2

公开(公告)日：2003-03-13

申请号：PCT/US2002/027684

申请日：2002-08-29

Applicant: ANALOG DEVICES, INC.

Inventor： SOERENSEN, Joern ,  KRIVACEK, Paul, D. ,  ALLEN, Michael ,  BANSE, Mark

IPC: G11C7/00

CPC classification number: G06F11/3636 ,  G06F1/04 ,  G06F1/08 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3869 ,  G06F9/4843 ,  G06F12/0842 ,  G06F12/0859 ,  G06F13/28 ,  G06F13/385 ,  G06F2213/3814 ,  H03L7/0802 ,  H03L7/095 ,  H03L7/183 ,  H04W88/06 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/151 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D10/24 ,  Y02D50/20 ,  Y02D70/1222 ,  Y02D70/124 ,  Y02D70/142 ,  Y02D70/144 ,  Y02D70/164 ,  Y10S331/02

Abstract: Methods and apparatus for accessing flash memory in a continued burst mode are provided. The apparatus includes a processor for executing instructions including memory access instructions, the processor generating a next access signal that indicates if a next memory access is in sequence with a current memory access, a memory having a continued burst mode of operation, and a bus interface for controlling access to the memory in response to the memory access instructions. The bus interface unit enables the continued burst mode of the memory while the next access signal is asserted.

Abstract translation: 提供了以连续突发模式访问闪存的方法和装置。 该装置包括用于执行包括存储器访问指令的指令的处理器，处理器产生下一个访问信号，该下一个访问信号指示下一个存储器访问是否与当前存储器访问顺序相关，具有连续突发操作模式的存储器以及总线接口 用于响应于存储器访问指令来控制对存储器的访问。 总线接口单元启用存储器的连续突发模式，同时确定下一个访问信号。

公开(公告)号：WO2003021439A1

公开(公告)日：2003-03-13

申请号：PCT/US2002/027670

申请日：2002-08-29

Applicant: ANALOG DEVICES, INC.

Inventor： BIRK, Palle ,  SOERENSEN, Joern ,  ALLEN, Michael ,  FRIDMAN, Jose

IPC: G06F9/48

CPC classification number: G06F11/3636 ,  G06F1/04 ,  G06F1/08 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3869 ,  G06F9/4843 ,  G06F12/0842 ,  G06F12/0859 ,  G06F13/28 ,  G06F13/385 ,  G06F2213/3814 ,  H03L7/0802 ,  H03L7/095 ,  H03L7/183 ,  H04W88/06 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/151 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D10/24 ,  Y02D50/20 ,  Y02D70/1222 ,  Y02D70/124 ,  Y02D70/142 ,  Y02D70/144 ,  Y02D70/164 ,  Y10S331/02

Abstract: Methods and apparatus are provided for operating an embedded processor system that includes a processor and a cache memory. The method includes filling one or more lines in the cache memory with data associated with a first task, executing the first task, and, in response to a cache miss during executing of the first task, performing a cache line fill operation and, during the cache line fill operation, executing a second task. The cache memory may notify the processor of the line fill operation by generating a processor interrupt or by notifying a task scheduler running on the processor.

Abstract translation: 提供了用于操作包括处理器和高速缓冲存储器的嵌入式处理器系统的方法和装置。 该方法包括在高速缓冲存储器中填充与第一任务相关联的数据，执行第一任务，以及响应于执行第一任务期间的高速缓存未命中，执行高速缓存行填充操作，并且在 缓存线填充操作，执行第二任务。 高速缓冲存储器可以通过产生处理器中断或通知在处理器上运行的任务调度器来通知处理器线路填充操作。