公开(公告)号：WO2011094323A1

公开(公告)日：2011-08-04

申请号：PCT/US2011/022590

申请日：2011-01-26

Applicant: APPLE INC. ,  IWAMOTO, Derek ,  SFARZO, Steven, J. ,  SCHMIDT, Ryan ,  CARTY, Derrick ,  COX, Keith

Inventor： IWAMOTO, Derek ,  SFARZO, Steven, J. ,  SCHMIDT, Ryan ,  CARTY, Derrick ,  COX, Keith

IPC: G06F1/32

CPC classification number: G06F1/3203 ,  G06F1/3275 ,  G11C5/141 ,  G11C5/148 ,  G11C11/4074 ,  Y02D10/14 ,  Y02D50/20

Abstract: A data processing system that uses memory power reduction in a sleep state. The system can include a volatile memory and at least one data input peripheral and a logic circuit that is configured to manage power consumption of the data processing system for a sleep of the system. The logic circuit can be coupled to the volatile memory and can be configured to turn off power to the volatile memory in response to an event, occurring during the sleep state, but to otherwise remain in the sleep state. The sleep state can be an ACPI complaint S3 sleep state in which the volatile memory, such as DRAM, is powered off after a period of user inactivity during the S3 sleep state.

Abstract translation: 一种在休眠状态下使用存储器功率降低的数据处理系统。 该系统可以包括易失性存储器和至少一个数据输入外设和逻辑电路，其被配置为管理数据处理系统对系统的睡眠的功耗。 逻辑电路可以耦合到易失性存储器，并且可以被配置为响应于在睡眠状态期间发生的事件而关闭到易失性存储器的电力，但是否则保持在睡眠状态。 睡眠状态可以是在S3睡眠状态期间在用户不活动的时段之后关闭易失性存储器（例如DRAM）的ACPI投诉S3休眠状态。

公开(公告)号：WO2015187246A1

公开(公告)日：2015-12-10

申请号：PCT/US2015/024653

申请日：2015-04-07

Applicant: APPLE INC.

Inventor： SMITH, Michael, J. ,  DE CESARE, Josh, P. ,  TRIPATHI, Brijesh ,  IWAMOTO, Derek ,  KEIL, Shane, J.

IPC: G06F13/38

CPC classification number: G06F13/4226 ,  G06F13/105 ,  G06F13/28 ,  G06F13/385 ,  G06F13/4022 ,  G06F13/4059

Abstract: An interface emulator for an IC is disclosed. An interface emulator includes a first first-in, first-out memory (FIFO) and a second FIFO. The first FIFO is coupled to receive data from an access port and a second FIFO coupled to receive data from at least one functional unit in the IC. The access port may be coupled to a device that is external to the IC. The external device may write information into the first FIFO, and this information may subsequently be read by a functional unit in the IC. Similarly, the functional unit may write information into the second FIFO, with the external device subsequently reading the information. Information may be written into the FIFOs in accordance with a predefined protocol. Thus, a particular type of interface may be emulated even though the physical connection and supporting circuitry for that interface is not otherwise implemented in the IC.

Abstract translation: 公开了一种用于IC的接口仿真器。 接口仿真器包括第一先入先出存储器（FIFO）和第二FIFO。 第一FIFO被耦合以从接入端口接收数据，并且第二FIFO被耦合以从IC中的至少一个功能单元接收数据。 访问端口可以耦合到IC外部的设备。 外部设备可以将信息写入第一FIFO，并且该信息随后可以由IC中的功能单元读取。 类似地，功能单元可以将信息写入第二FIFO，随后外部设备读取信息。 可以根据预定义的协议将信息写入FIFO。 因此，即使在IC中没有实现用于该接口的物理连接和支持电路，也可以模拟特定类型的接口。