公开(公告)号：WO2018026709A1

公开(公告)日：2018-02-08

申请号：PCT/US2017/044668

申请日：2017-07-31

Applicant: APPLE INC.

Inventor： GULATI, Manu ,  HOLLAND, Peter F. ,  MACHNICKI, Erik P. ,  JETER, Robert E. ,  NOTANI, Rakesh L. ,  PARIK, Neeraj ,  SCHAUB, Marc A.

IPC: G06F13/16

CPC classification number: G06F3/0656 ,  G06F3/0604 ,  G06F3/0683 ,  G06F13/1673 ,  G11C11/40615

Abstract: In some embodiments, a system includes a memory system, a real-time computing device, and a controller. The real-time computing device stores data within a local buffer having a corresponding storage threshold, where the data satisfies the storage threshold, and where the storage threshold is based on a latency of the memory system and an expected rate of utilization of the data of the local buffer. The controller detects that the memory system should perform an operation, where the memory system is unavailable to the real-time computing device during the operation. In response to detecting that an amount of time for the operation exceeds an amount of time corresponding to the storage threshold, the controller overrides the storage threshold. The controller may override the storage threshold by modifying the storage threshold and by overriding a default priority for access requests of the real-time computing device to the memory system.

Abstract translation: 在一些实施例中，系统包括存储器系统，实时计算设备和控制器。 实时计算设备将数据存储在具有对应的存储阈值的本地缓冲区内，其中数据满足存储阈值，并且其中存储阈值基于存储器系统的等待时间和预期的数据利用率 本地缓冲区。 控制器检测到存储器系统应当执行操作，其中存储器系统在操作期间对于实时计算设备不可用。 响应于检测到操作的时间量超过对应于存储阈值的时间量，控制器覆盖存储阈值。 控制器可以通过修改存储阈值并且通过超越实时计算设备对存储器系统的访问请求的默认优先级来覆盖存储阈值。

公开(公告)号：WO2022031840A1

公开(公告)日：2022-02-10

申请号：PCT/US2021/044531

申请日：2021-08-04

Applicant: APPLE INC.

Inventor： JETER, Robert E. ,  NOTANI, Rakesh L. ,  HSIUNG, Kai Lun ,  MALLADI, Venkata Ramana ,  RANJAN, Rahul ,  KORADA, Naveen Kumar

IPC: G06F13/16 ,  G06F11/1076 ,  G06F13/1689 ,  G11C2207/2254 ,  G11C7/10 ,  G11C7/22

Abstract: A memory subsystem and method for performing calibrations therein is disclosed. A memory subsystem includes a memory controller coupled to a memory by a plurality of signal paths. The memory controller is configured to perform an initial calibration to determine respective eye patterns corresponding to the ones of the plurality of signal paths. For a subsequent calibrations, updated eye patterns are determined for a subset of the plurality of signal paths. Remaining ones of the plurality of signal paths (not included in the subset), are not active during the subsequent calibrations. Updated eye patterns for the remaining ones of the plurality of signal paths are determined based on information obtained during the initial calibration and information from signal paths in the subset designated proxies for the remaining ones of the plurality of signal paths.

公开(公告)号：WO2018052712A1

公开(公告)日：2018-03-22

申请号：PCT/US2017/049290

申请日：2017-08-30

Applicant: APPLE INC.

Inventor： JETER, Robert E. ,  DENG, Liang ,  HSIUNG, Kai Lun ,  GULATI, Manu ,  NOTANI, Rakesh L. ,  BISWAS, Sukalpa ,  MALLADI, Venkata Ramana ,  MATHEWS, Gregory S. ,  ZHENG, Enming ,  FAURE, Fabien S.

IPC: G06F13/16 ,  G06F13/42

CPC classification number: G06F3/0634 ,  G06F1/08 ,  G06F1/324 ,  G06F3/0625 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/0673 ,  G06F3/0683 ,  G06F13/1689 ,  G06F13/4243 ,  Y02D10/14 ,  Y02D10/151

Abstract: Systems, apparatuses, and methods for improved memory controller power management techniques. An apparatus includes control logic, one or more memory controller(s), and one or more memory devices. If the amount of traffic and/or queue depth for a given memory controller falls below a threshold, the clock frequency supplied to the given memory controller and corresponding memory device(s) is reduced. In one embodiment, the clock frequency is reduced by one half. If the amount of traffic and/or queue depth rises above the threshold, then the clock frequency is increased back to its original frequency. The clock frequency may be adjusted by doubling the divisor used by a clock divider, which enables fast switching between the original rate and the reduced rate. This in turn allows for more frequent switching between the low power and normal power states, resulting in the memory controller and memory device operating more efficiently.

Abstract translation: 用于改善存储器控制器功率管理技术的系统，设备和方法。 一种设备包括控制逻辑，一个或多个存储器控制器和一个或多个存储器设备。 如果给定存储器控制器的通信量和/或队列深度的量下降到阈值以下，则提供给给定存储器控制器和相应存储器设备的时钟频率被降低。 在一个实施例中，时钟频率减半。 如果业务量和/或队列深度增加到阈值以上，则时钟频率增加回到其原始频率。 时钟频率可以通过将时钟分频器使用的除数加倍来调整，这可以在原始速率和降低的速率之间进行快速切换。 这反过来又允许在低功率状态和正常功率状态之间更频繁地切换，从而导致存储器控制器和存储器设备更高效地工作。