公开(公告)号：WO2019136986A1

公开(公告)日：2019-07-18

申请号：PCT/CN2018/099765

申请日：2018-08-09

申请人： 江苏华存电子科技有限公司

发明人： 陈育鸣 ,  李庭育 ,  魏智汎 ,  洪振洲

IPC分类号： G06F13/16

CPC分类号： G06F3/0625 ,  G06F3/0679 ,  G06F13/1668 ,  Y02D10/14 ,  Y02D10/151

摘要： 一种用于分散与降低非易失性储存装置峰值电流与功耗的方法，所述非易失性储存装置包括控制器芯片(1)、存储介质(2)和多个闪存芯片，存储介质(2)中存储程序代码，存储介质(2)连接控制器芯片(1)，控制器芯片(1)分别连接多个闪存芯片，通过随时间分布闪存芯片的操作，特别是在不同时间点向每个闪存芯片发送命令，降低了整个系统的峰值电流。

公开(公告)号：WO2019118096A1

公开(公告)日：2019-06-20

申请号：PCT/US2018/059533

申请日：2018-11-07

申请人： QUALCOMM INCORPORATED

发明人： PATEL, Dhaval ,  PACKER ALI, Dhamim ,  GORANTLA, Venkata Vara Prasad ,  NABAR, Anushka Mihir

IPC分类号： G06F12/0868 ,  G06F1/3206 ,  G06F9/4401 ,  G06F1/3234 ,  G06F1/3287 ,  G11C5/14 ,  G11C14/00 ,  G06F21/57 ,  G06F21/78 ,  G06F21/79 ,  G06F12/14 ,  G06F1/3228

CPC分类号： G06F3/0625 ,  G06F1/3228 ,  G06F1/3275 ,  G06F1/3287 ,  G06F1/3296 ,  G06F3/0623 ,  G06F3/0634 ,  G06F3/0683 ,  G06F9/4418 ,  G06F12/0868 ,  G06F12/1408 ,  G06F21/57 ,  G06F21/572 ,  G06F21/575 ,  G06F21/78 ,  G06F21/79 ,  G06F2212/401 ,  G11C5/143 ,  G11C14/0018

摘要： A system and a method for power mode selection in a portable computing device is provided herein. The system and method may comprise operations for operating the portable computing device in a normal mode. The normal mode may utilize a plurality of memory banks within a volatile memory, such as a random access memory (''RAM''), where the memory banks are powered-up and operable to store data. The system and method may further identify a memory segment within the plurality of memory banks, store the memory segment as a stored memory segment (where the stored memory segment is operable to restore the memory segment), and power down the powered-up memory bank associated with the memory segment. Further aspects are described herein.

公开(公告)号：WO2019050514A1

公开(公告)日：2019-03-14

申请号：PCT/US2017/050272

申请日：2017-09-06

申请人： HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

发明人： JABORI, Monji G. ,  VU, Jonathan

IPC分类号： G06F13/42

CPC分类号： G06F3/0625 ,  G06F3/0634 ,  G06F3/0677 ,  G06F13/42

摘要： A system may include a computing device. The computing device may include an optical disc drive (ODD) bay, wherein an ODD is not present in the ODD bay. The system may further include an ODD connector. The system may also include an external serial AT attachment (eSATA) device located in an opening of the ODD bay for housing the non-present ODD and coupled to the computing device by the ODD connector at the ODD bay.

公开(公告)号：WO2018128714A1

公开(公告)日：2018-07-12

申请号：PCT/US2017/061657

申请日：2017-11-15

申请人： QUALCOMM INCORPORATED

发明人： JAIN, Nikhil ,  SHAMBHU, Ankit ,  RAO, Umesh ,  MOLA, Srinivasarao

IPC分类号： G11C7/10 ,  G11C8/12

CPC分类号： G06F3/0625 ,  G06F3/0634 ,  G06F3/0659 ,  G06F3/0673 ,  G11C7/1045 ,  G11C8/12

摘要： Systems and method are directed to reducing power consumption of a memory based on enabling partial page access. Based on system conditions such as operating frequency, access size for one or more memory access requests are determined. The access size is programmed in a mode register of the memory and one or more commands are issued for accessing the memory based on the programmed access size. Alternatively, the access sizes are specified within the one or more commands issued to the memory for accessing partial pages. Activating only the portion of a page corresponding to the partial page access reduces power consumption.

公开(公告)号：WO2018052712A1

公开(公告)日：2018-03-22

申请号：PCT/US2017/049290

申请日：2017-08-30

申请人： APPLE INC.

发明人： JETER, Robert E. ,  DENG, Liang ,  HSIUNG, Kai Lun ,  GULATI, Manu ,  NOTANI, Rakesh L. ,  BISWAS, Sukalpa ,  MALLADI, Venkata Ramana ,  MATHEWS, Gregory S. ,  ZHENG, Enming ,  FAURE, Fabien S.

IPC分类号： G06F13/16 ,  G06F13/42

CPC分类号： G06F3/0634 ,  G06F1/08 ,  G06F1/324 ,  G06F3/0625 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/0673 ,  G06F3/0683 ,  G06F13/1689 ,  G06F13/4243 ,  Y02D10/14 ,  Y02D10/151

摘要： Systems, apparatuses, and methods for improved memory controller power management techniques. An apparatus includes control logic, one or more memory controller(s), and one or more memory devices. If the amount of traffic and/or queue depth for a given memory controller falls below a threshold, the clock frequency supplied to the given memory controller and corresponding memory device(s) is reduced. In one embodiment, the clock frequency is reduced by one half. If the amount of traffic and/or queue depth rises above the threshold, then the clock frequency is increased back to its original frequency. The clock frequency may be adjusted by doubling the divisor used by a clock divider, which enables fast switching between the original rate and the reduced rate. This in turn allows for more frequent switching between the low power and normal power states, resulting in the memory controller and memory device operating more efficiently.

摘要翻译： 用于改善存储器控制器功率管理技术的系统，设备和方法。 一种设备包括控制逻辑，一个或多个存储器控制器和一个或多个存储器设备。 如果给定存储器控制器的通信量和/或队列深度的量下降到阈值以下，则提供给给定存储器控制器和相应存储器设备的时钟频率被降低。 在一个实施例中，时钟频率减半。 如果业务量和/或队列深度增加到阈值以上，则时钟频率增加回到其原始频率。 时钟频率可以通过将时钟分频器使用的除数加倍来调整，这可以在原始速率和降低的速率之间进行快速切换。 这反过来又允许在低功率状态和正常功率状态之间更频繁地切换，从而导致存储器控制器和存储器设备更高效地工作。

公开(公告)号：WO2018031366A1

公开(公告)日：2018-02-15

申请号：PCT/US2017/045292

申请日：2017-08-03

申请人： INTEL CORPORATION

发明人： SAINT-HILAIRE, Ylian ,  MENDELSON, Tsippy

IPC分类号： G06F9/44

CPC分类号： G06F3/0625 ,  G06F1/3287 ,  G06F3/0655 ,  G06F3/0679 ,  G06F16/9566 ,  G06F16/958

摘要： A system and method are disclosed for remote management, including systems and methods for hosting web applications within remote management hardware and/or firmware. In one embodiment, a system includes a microcontroller to configure a processor, the microcontroller including a memory. The system further includes a network interface coupled to the microcontroller, the network interface to send and receive communications with an external device. The system further includes a non-volatile memory to store computer executable instructions to be executed by the microcontroller, and a power supply to provide power to the microcontroller, the network interface, and the non-volatile memory regardless of the power state of the processor, wherein the microcontroller is to provide a web server to receive and process HyperterText Transfer Protocol (HTTP) requests from the external device.

摘要翻译： 公开了一种用于远程管理的系统和方法，包括用于在远程管理硬件和/或固件内托管web应用的系统和方法。 在一个实施例中，系统包括用于配置处理器的微控制器，该微控制器包括存储器。 该系统还包括耦合到微控制器的网络接口，该网络接口用于发送和接收与外部设备的通信。 该系统还包括用于存储要由微控制器执行的计算机可执行指令的非易失性存储器以及用于向微控制器，网络接口和非易失性存储器提供功率的电源，而与处理器的功率状态无关 ，其中微控制器将提供Web服务器以接收和处理来自外部设备的HyperterText传输协议（HTTP）请求。

公开(公告)号：WO2017210143A1

公开(公告)日：2017-12-07

申请号：PCT/US2017/034889

申请日：2017-05-28

申请人： INTEL CORPORATION

发明人： BLANKENSHIP, Robert G. ,  STEELY, Simon C. ,  SURY, Samantika S.

IPC分类号： G06F12/02

CPC分类号： G06F3/0605 ,  G06F3/0625 ,  G06F3/0659 ,  G06F3/0673 ,  G06F12/0808 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0824 ,  G06F12/0826 ,  G06F12/0831 ,  G06F12/0842 ,  G06F2212/1028 ,  G06F2212/1048 ,  Y02D10/13

摘要： Systems, methods, and apparatuses are directed to requesting access to a memory address; storing an identification of the memory address in a data structure; receiving a first request for access to the memory address, the request comprising a reference to a second processor core; storing the reference to the second processor in the data structure; receiving a second request for access to the memory address, the second request comprising a reference to a third processor core; determining, based on the data structure, that the third processor core is different from the second processor core; and responding to the second request without buffering the second request.

摘要翻译： 系统，方法和设备涉及请求访问存储器地址; 将存储器地址的标识存储在数据结构中; 接收访问所述存储器地址的第一请求，所述请求包括对第二处理器核心的引用; 将对第二处理器的引用存储在数据结构中; 接收访问所述存储器地址的第二请求，所述第二请求包括对第三处理器核心的引用; 基于所述数据结构确定所述第三处理器核不同于所述第二处理器核; 并在不缓冲第二个请求的情况下响应第二个请求。

公开(公告)号：WO2017136099A2

公开(公告)日：2017-08-10

申请号：PCT/US2017/012514

申请日：2017-01-06

申请人： QUALCOMM INCORPORATED

发明人： ALAVOINE, Olivier ,  LEE, Sejoong ,  KAZI, Tauseef ,  BOOTH, Simon ,  REGINI, Edoardo ,  JAKUSHOKAS, Renatas ,  PATODIA, Saurabh ,  GEMAR, Jeffrey ,  LO, Haw-Jing ,  CHAMARTY, Vinod ,  ANDREEV, Boris ,  SHEN, Tao ,  BHASKARA, Aravind ,  WANG, Wenbiao ,  MOLLOY, Stephen

CPC分类号： G06F3/0659 ,  G06F1/3275 ,  G06F3/0625 ,  G06F3/0673 ,  G06F12/08 ,  Y02D10/13 ,  Y02D10/14

摘要： Various aspects include methods for managing memory subsystems on a computing device. Various aspect methods may include determining a period of time to force a memory subsystem on the computing device into a low power mode, inhibiting memory access requests to the memory subsystem during the determined period of time, forcing the memory subsystem into the low power mode for the determined period of time, and executing the memory access requests to the memory subsystem inhibited during the determined period of time in response to expiration of the determined period of time.

摘要翻译： 各种方面包括用于管理计算设备上的存储器子系统的方法。 各种方面方法可以包括确定强制计算设备上的存储器子系统进入低功率模式的时间段，在确定的时间段期间禁止对存储器子系统的存储器访问请求，迫使存储器子系统进入低功率模式 所确定的时间周期，并且响应于所确定的时间段的期满，在所确定的时间段期间向存储器子系统执行存储器访问请求。

公开(公告)号：WO2017106652A3

公开(公告)日：2017-07-13

申请号：PCT/US2016067187

申请日：2016-12-16

申请人： MICROSEMI STORAGE SOLUTIONS (U S ) INC

发明人： KUMAR AMRENDRA ,  PRASAD JANARDAN ,  CLINTON DAVID JOSEPH

IPC分类号： G06F1/32 ,  G06F3/06

CPC分类号： G06F1/3225 ,  G06F1/3206 ,  G06F1/3253 ,  G06F1/3275 ,  G06F1/3287 ,  G06F3/0625 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

摘要： A power-saving method and circuit in a data processing device comprising a data buffer. Read commands associated with a data source and a data destination are received at the data processing device. The read commands are accumulated until an amount of read data associated with the read commands is greater than a predefined threshold. When the amount of read data is less than the predefined threshold and the data buffer is empty, the data buffer is signaled to enter or to maintain a sleep mode. When the amount of read data is at least the predefined threshold, the data buffer is signaled to exit the sleep mode following a preconfigured delay. Processing of the read commands and read data in respective pipelines is monitored to time exiting of the buffer from the sleep mode for arrival of the read data. Sleep mode use and thus power saving are optimized.

摘要翻译： 包括数据缓冲器的数据处理设备中的节能方法和电路。 在数据处理设备处接收与数据源和数据目的地相关联的读取命令。 读取命令被累积，直到与读取命令相关联的读取数据量大于预定义阈值。 当读取的数据量小于预定义的阈值并且数据缓冲器为空时，数据缓冲器被发送信号以进入或维持睡眠模式。 当读取的数据量至少是预定义的阈值时，数据缓冲器被发送信号以在预先配置的延迟之后退出睡眠模式。 监视各个管线中读取命令和读取数据的处理，以使缓冲器从休眠模式退出以便读取数据到达。 使用睡眠模式，从而优化节能。

公开(公告)号：WO2017106652A2

公开(公告)日：2017-06-22

申请号：PCT/US2016/067187

申请日：2016-12-16

申请人： MICROSEMI STORAGE SOLUTIONS (U.S.), INC.

发明人： KUMAR, Amrendra ,  PRASAD, Janardan ,  CLINTON, David Joseph

IPC分类号： G06F1/32

CPC分类号： G06F1/3225 ,  G06F1/3206 ,  G06F1/3253 ,  G06F1/3275 ,  G06F1/3287 ,  G06F3/0625 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

摘要： A power-saving method and circuit in a data processing device comprising a data buffer. Read commands associated with a data source and a data destination are received at the data processing device. The read commands are accumulated until an amount of read data associated with the read commands is greater than a predefined threshold. When the amount of read data is less than the predefined threshold and the data buffer is empty, the data buffer is signaled to enter or to maintain a sleep mode. When the amount of read data is at least the predefined threshold, the data buffer is signaled to exit the sleep mode following a preconfigured delay. Processing of the read commands and read data in respective pipelines is monitored to time exiting of the buffer from the sleep mode for arrival of the read data. Sleep mode use and thus power saving are optimized.

摘要翻译： 包括数据缓冲器的数据处理设备中的节能方法和电路。 在数据处理设备处接收与数据源和数据目的地相关联的读取命令。 读取命令被累积，直到与读取命令相关联的读取数据量大于预定义阈值。 当读取的数据量小于预定义的阈值并且数据缓冲器为空时，数据缓冲器被发送信号以进入或维持睡眠模式。 当读取的数据量至少是预定义的阈值时，数据缓冲器被发送信号以在预先配置的延迟之后退出睡眠模式。 监视各个管线中读取命令和读取数据的处理，以使缓冲器从休眠模式退出以便读取数据到达。 睡眠模式的使用，从而优化节能。