公开(公告)号：WO2013181166A1

公开(公告)日：2013-12-05

申请号：PCT/US2013/042926

申请日：2013-05-28

Applicant: CBRITE INC.

Inventor： SHIEH, Chan-long ,  YU, Gang ,  FOONG, Fatt ,  LEE, Liu-chung

IPC: G02F1/1343

CPC classification number: G02F1/134363 ,  G02F1/13439 ,  G02F1/1368 ,  G02F2001/134372 ,  G02F2001/136231 ,  G02F2001/136236 ,  H01L27/1225 ,  H01L27/1288

Abstract: A method of fabricating a TFT and IPS with reduced masking operations includes a substrate, a gate, a layer of gate dielectric on the gate and surrounding substrate surface and a semiconducting metal oxide on the gate dielectric. A channel protection layer overlies the gate to define a channel area in the semiconducting metal oxide. A S/D metal layer is patterned on the channel protection layer and a portion of the exposed semiconducting metal oxide to define an IPS area. An organic dielectric material is patterned on the S/D terminals and at an opposed side of the IPS area. The S/D metal is etched to expose the semiconducting metal oxide defining a first IPS electrode. A passivation layer covers the first electrode and a layer of transparent conductive material is patterned on the passivation layer to define a second IPS electrode overlying the first electrode.

Abstract translation: 制造具有减小的掩模操作的TFT和IPS的方法包括在栅极和周围的衬底表面上的衬底，栅极，栅极电介质层和栅极电介质上的半导体金属氧化物。 沟道保护层覆盖栅极以限定半导体金属氧化物中的沟道区。 在沟道保护层和暴露的半导体金属氧化物的一部分上形成S / D金属层以限定IPS区域。 在S / D端子和IPS区域的相对侧上构图有机电介质材料。 蚀刻S / D金属以暴露限定第一IPS电极的半导体金属氧化物。 钝化层覆盖第一电极，并且在钝化层上图案化透明导电材料层，以限定覆盖第一电极的第二IPS电极。