公开(公告)号：WO2012170160A1

公开(公告)日：2012-12-13

申请号：PCT/US2012/038075

申请日：2012-05-16

Applicant: CBRITE INC. ,  SHIEH, Chan-long ,  YU, Gang ,  FOONG, Fatt

Inventor： SHIEH, Chan-long ,  YU, Gang ,  FOONG, Fatt

IPC: H01L21/36 ,  H01L21/44 ,  H01L21/465

CPC classification number: H01L29/7869 ,  H01L21/428 ,  H01L29/45 ,  H01L29/66969 ,  H01L29/78606

Abstract: A method of forming ohmic source/drain contacts in a metal oxide semiconductor thin film transistor includes providing a gate, a gate dielectric, a high carrier concentration metal oxide semiconductor active layer with a band gap and spaced apart source/drain metal contacts in a thin film transistor configuration. The spaced apart source/drain metal contacts define a channel region in the active layer. An oxidizing ambient is provided adjacent the channel region and the gate and the channel region are heated in the oxidizing ambient to reduce the carrier concentration in the channel area. Alternatively or in addition each of the source/drain contacts includes a very thin layer of low work function metal positioned on the metal oxide semiconductor active layer and a barrier layer of high work function metal is positioned on the low work function metal.

Abstract translation: 在金属氧化物半导体薄膜晶体管中形成欧姆源极/漏极接触的方法包括：提供栅极，栅极电介质，具有带隙的高载流子浓度金属氧化物半导体有源层和间隔开的薄/弱金属氧化物半导体有源层 薄膜晶体管配置。 间隔开的源极/漏极金属触点限定有源层中的沟道区。 在沟道区域附近提供氧化环境，并且在氧化环境中加热栅极和沟道区域以降低沟道区域中的载流子浓度。 或者或另外每个源极/漏极触点包括位于金属氧化物半导体有源层上的非常薄的低功函数金属层，并且高功函数金属的阻挡层位于低功函数金属上。

公开(公告)号：WO2015073502A1

公开(公告)日：2015-05-21

申请号：PCT/US2014/065161

申请日：2014-11-12

Applicant: CBRITE INC.

Inventor： YU, Gang ,  SHIEH, Chan-Long ,  MUSOLF, Juergen ,  FOONG, Fatt ,  XIAO, Tian

IPC: H01L21/36 ,  H01L21/38 ,  H01L29/86

CPC classification number: H01L27/1203 ,  H01L21/02565 ,  H01L21/02664 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/7869

Abstract: A method of fabricating a high mobility semiconductor metal oxide thin film transistor including the steps of depositing a layer of semiconductor metal oxide material, depositing a blanket layer of etch-stop material on the layer of MO material, and patterning a layer of source/drain metal on the blanket layer of etch-stop material including etching the layer of source/drain metal into source/drain terminals positioned to define a channel area in the semiconductor metal oxide layer. The etch-stop material being electrically conductive in a direction perpendicular to the plane of the blanket layer at least under the source/drain terminals to provide electrical contact between each of the source/drain terminals and the layer of semiconductor metal oxide material. The etch-stop material is also chemical robust to protect the layer of semiconductor metal oxide channel material during the etching process.

Abstract translation: 一种制造高迁移率半导体金属氧化物薄膜晶体管的方法，包括以下步骤：沉积半导体金属氧化物材料层，在MO材料层上沉积蚀刻停止材料的覆盖层，以及图案化源/漏层 包括将源极/漏极金属层蚀刻成定位成限定半导体金属氧化物层中的沟道区域的源极/漏极端子的蚀刻停止材料的覆盖层上的金属。 蚀刻停止材料至少在源极/漏极端子之下在垂直于覆盖层的平面的方向上导电，以提供每个源极/漏极端子和半导体金属氧化物材料层之间的电接触。 蚀刻停止材料也是化学稳固的，以在蚀刻工艺期间保护半导体金属氧化物沟道材料层。

公开(公告)号：WO2014189681A2

公开(公告)日：2014-11-27

申请号：PCT/US2014/037191

申请日：2014-05-07

Applicant: CBRITE INC.

Inventor： SHIEH, Chan-long ,  YU, Gang ,  FOONG, Fatt ,  MUSOLF, Juergen

IPC: H01L21/465

CPC classification number: H01L29/66969 ,  H01L21/02063 ,  H01L21/02565 ,  H01L21/02631 ,  H01L21/76805 ,  H01L21/76814 ,  H01L21/76895 ,  H01L27/1225 ,  H01L29/247 ,  H01L29/42384 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66742 ,  H01L29/78603 ,  H01L29/78606 ,  H01L29/78618 ,  H01L29/78693 ,  H01L29/78696 ,  H01L2021/775

Abstract: A method of fabricating a stable high mobility amorphous MOTFT includes a step of providing a substrate with a gate formed thereon and a gate dielectric layer positioned over the gate. A carrier transport structure is deposited by sputtering on the gate dielectric layer. The carrier transport structure includes a layer of amorphous high mobility metal oxide adjacent the gate dielectric and a relatively inert protective layer of material deposited on the layer of amorphous high mobility metal oxide both deposited without oxygen and in situ . The layer of amorphous metal oxide has a mobility above 40 cm 2 /Vs and a carrier concentration in a range of approximately 10 18 cm -3 to approximately 5xl0 19 cm -3 . Source/drain contacts are positioned on the protective layer and in electrical contact therewith.

Abstract translation: 制造稳定的高迁移率无定形MOTFT的方法包括提供其上形成有栅极的基板和位于栅极上方的栅介质层的步骤。 通过溅射将载流子传输结构沉积在栅极介电层上。 载流子传输结构包括邻近栅极电介质的非晶高迁移率金属氧化物层，以及沉积在无氧和原位沉积的无定形高迁移率金属氧化物层上的相对惰性的材料保护层。 无定形金属氧化物层的迁移率高于40cm 2 / Vs，载流子浓度在约1018cm-3至约5×1019cm-3的范围内。 源极/漏极触点位于保护层上并与其电接触。

公开(公告)号：WO2013019910A1

公开(公告)日：2013-02-07

申请号：PCT/US2012/049238

申请日：2012-08-02

Applicant: CBRITE INC. ,  SHIEH, Chan-Long ,  YU, Gang ,  FOONG, Fatt

Inventor： SHIEH, Chan-Long ,  YU, Gang ,  FOONG, Fatt

IPC: H01L29/10

CPC classification number: H01L29/7869 ,  H01L21/02554 ,  H01L21/02565

Abstract: A method of fabricating MO TFTs on transparent substrates by positioning opaque gate metal on the front surface of the substrate defining a gate area, depositing gate dielectric material on the front surface of the substrate, overlying the gate metal and a surrounding area, and depositing metal oxide semiconductor material on the gate dielectric material. Depositing etch stop material on the semiconductor material. Positioning photoresist on the etch stop material, the etch stop material and the photoresist being selectively removable, and the photoresist defining an isolation area in the semiconductor material. Removing uncovered portions of the etch stop. Exposing the photoresist from the rear surface of the substrate using the gate metal as a mask and removing exposed portions so as to leave the etch stop material uncovered except for a portion overlying and aligned with the gate metal. Etching uncovered portions of the semiconductor material to isolate the TFT. Using the photoresist, selectively etching the etch stop layer to leave a portion overlying and aligned with the gate metal and defining a channel area in the semiconductor material. Depositing and patterning conductive material on the etch stop layer and on the semiconductor material to form source and drain areas on opposed sides of the channel area.

Abstract translation: 一种在透明基板上制造MO TFT的方法，该方法是通过在形成栅极区域的衬底的前表面上定位不透明栅极金属，在衬底的前表面上沉积栅介电材料，覆盖栅极金属和周围区域，并沉积金属 氧化物半导体材料。 在半导体材料上沉积蚀刻停止材料。 将光致抗蚀剂定位在蚀刻停止材料上，蚀刻停止材料和光致抗蚀剂可选择性地移除，并且光刻胶在半导体材料中限定隔离区域。 去除蚀刻停止件的未覆盖部分。 使用栅极金属作为掩模从基板的后表面露出光致抗蚀剂，并除去暴露部分，以使除蚀刻停止材料未被覆盖，除了覆盖并与栅极金属对准的部分之外。 蚀刻半导体材料的未覆盖部分以隔离TFT。 使用光致抗蚀剂，选择性地蚀刻蚀刻停止层以留下覆盖并与栅极金属对准的部分并限定半导体材料中的沟道区域。 在蚀刻停止层和半导体材料上沉积和图案化导电材料以在沟道区域的相对侧上形成源极和漏极区域。

公开(公告)号：WO2015142525A1

公开(公告)日：2015-09-24

申请号：PCT/US2015/018807

申请日：2015-03-04

Applicant: CBRITE INC.

Inventor： YU, Gang ,  SHIEH, Chan-Long ,  WANG, Guangming ,  FOONG, Fatt

IPC: H01L21/70 ,  H01L27/32 ,  H01L51/52

CPC classification number: H01L27/3244 ,  H01L27/1259 ,  H01L27/322 ,  H01L29/78603 ,  H01L51/003 ,  H01L51/0097 ,  H01L51/5246 ,  H01L51/56 ,  H01L2227/323 ,  H01L2251/5338

Abstract: A process of fabricating a flexible TFT back-panel on a glass support includes a step of providing a flat glass support member sufficiently thick to prevent bending during the processing. A layer of etch stop material is positioned on the upper surface of the glass support member and an insulating buffer layer is positioned on the layer of etch stop material. A TFT back-panel is positioned on the insulating buffer layer and a flexible plastic carrier is affixed to the TFT back-panel. The glass support member is etched away, whereby a flexible TFT back-panel is provided. The TFT back-panel can include a matrix of either OLED cells or LCD cells.

Abstract translation: 在玻璃支架上制造柔性TFT背板的工艺包括提供足够厚的平板玻璃支撑件以防止加工过程中弯曲的步骤。 一层蚀刻停止材料定位在玻璃支撑构件的上表面上，并且绝缘缓冲层位于蚀刻停止材料层上。 TFT背板位于绝缘缓冲层上，柔性塑料载体固定在TFT后面板上。 蚀刻玻璃支撑构件，由此提供柔性TFT背面板。 TFT背面板可以包括OLED单元或LCD单元的矩阵。

公开(公告)号：WO2015069710A1

公开(公告)日：2015-05-14

申请号：PCT/US2014/064045

申请日：2014-11-05

Applicant: CBRITE INC.

Inventor： SHIEH, Chan-Long ,  YU, Gang ,  FOONG, Fatt

IPC: H01L29/786 ,  H01L27/32 ,  H01L21/027

CPC classification number: H01L29/78696 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/707 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1288 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/7869

Abstract: A method of fabricating MO TFTs includes positioning opaque gate metal on a transparent substrate to define a gate area. Depositing gate dielectric material overlying the gate metal and a surrounding area, and depositing metal oxide semiconductor material thereon. Depositing etch stop material on the semiconductor material. Positioning photoresist defining an isolation area in the semiconductor material, the etch stop material and the photoresist being selectively removable. Exposing the photoresist from the rear surface of the substrate and removing exposed portions to leave the etch stop material uncovered except for a portion overlying and aligned with the gate metal. Etching uncovered portions of the semiconductor material to isolate the TFT. Using the photoresist, selectively etching the etch stop layer to leave a portion overlying and aligned with the gate metal and defining a channel area in the semiconductor material. Depositing and patterning conductive material to form source and drain areas.

Abstract translation: 制造MO TFT的方法包括将不透明栅极金属定位在透明基板上以限定栅极区域。 覆盖栅极金属和周围区域的沉积栅介质材料，以及在其上沉积金属氧化物半导体材料。 在半导体材料上沉积蚀刻停止材料。 在半导体材料中定义隔离区域的定位光刻胶，蚀刻停止材料和光致抗蚀剂被选择性地移除。 从基板的后表面露出光致抗蚀剂，除去暴露的部分以使蚀刻停止材料除外覆盖并与栅极金属对准的部分。 蚀刻半导体材料的未覆盖部分以隔离TFT。 使用光致抗蚀剂，选择性地蚀刻蚀刻停止层以留下覆盖并与栅极金属对准的部分并且限定半导体材料中的沟道区域。 沉积和图案化导电材料以形成源极和漏极区域。

公开(公告)号：WO2013181166A1

公开(公告)日：2013-12-05

申请号：PCT/US2013/042926

申请日：2013-05-28

Applicant: CBRITE INC.

Inventor： SHIEH, Chan-long ,  YU, Gang ,  FOONG, Fatt ,  LEE, Liu-chung

IPC: G02F1/1343

CPC classification number: G02F1/134363 ,  G02F1/13439 ,  G02F1/1368 ,  G02F2001/134372 ,  G02F2001/136231 ,  G02F2001/136236 ,  H01L27/1225 ,  H01L27/1288

Abstract: A method of fabricating a TFT and IPS with reduced masking operations includes a substrate, a gate, a layer of gate dielectric on the gate and surrounding substrate surface and a semiconducting metal oxide on the gate dielectric. A channel protection layer overlies the gate to define a channel area in the semiconducting metal oxide. A S/D metal layer is patterned on the channel protection layer and a portion of the exposed semiconducting metal oxide to define an IPS area. An organic dielectric material is patterned on the S/D terminals and at an opposed side of the IPS area. The S/D metal is etched to expose the semiconducting metal oxide defining a first IPS electrode. A passivation layer covers the first electrode and a layer of transparent conductive material is patterned on the passivation layer to define a second IPS electrode overlying the first electrode.

Abstract translation: 制造具有减小的掩模操作的TFT和IPS的方法包括在栅极和周围的衬底表面上的衬底，栅极，栅极电介质层和栅极电介质上的半导体金属氧化物。 沟道保护层覆盖栅极以限定半导体金属氧化物中的沟道区。 在沟道保护层和暴露的半导体金属氧化物的一部分上形成S / D金属层以限定IPS区域。 在S / D端子和IPS区域的相对侧上构图有机电介质材料。 蚀刻S / D金属以暴露限定第一IPS电极的半导体金属氧化物。 钝化层覆盖第一电极，并且在钝化层上图案化透明导电材料层，以限定覆盖第一电极的第二IPS电极。

公开(公告)号：WO2011056294A1

公开(公告)日：2011-05-12

申请号：PCT/US2010/048264

申请日：2010-09-09

Applicant: CBRITE INC. ,  SHIEH, Chan-Long ,  FOONG, Fatt ,  YU, Gang

Inventor： SHIEH, Chan-Long ,  FOONG, Fatt ,  YU, Gang

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L27/1288 ,  H01L27/1214 ,  H01L27/1225 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/7869

Abstract: A method of fabricating a thin film transistor for an active matrix display using reduced masking operations includes patterning a gate on a substrate. A gate dielectric is formed over the gate and a semiconducting metal oxide is deposited on the gate dielectric. A channel protection layer is patterned on the semiconducting metal oxide overlying the gate to define a channel area and to expose the remaining semiconducting metal oxide. A source/drain metal layer is deposited on the structure and etched through to the channel protection layer above the gate to separate the source/drain metal layer into source and drain terminals and the source/drain metal layer and the semiconducting metal oxide are etched through at the periphery to isolate the transistor. A nonconductive spacer is patterned on the transistor and portions of the surrounding source/drain metal layer.

Abstract translation: 使用减少的掩模操作制造用于有源矩阵显示器的薄膜晶体管的方法包括在衬底上图形化栅极。 在栅极上形成栅极电介质，并且在栅极电介质上沉积半导体金属氧化物。 将通道保护层图案化在覆盖栅极的半导体金属氧化物上，以限定通道区域并露出剩余的半导体金属氧化物。 源极/漏极金属层沉积在结构上并蚀刻到栅极上方的沟道保护层，以将源极/漏极金属层分离成源极和漏极端子，并且源/漏极金属层和半导体金属氧化物被蚀刻通过 在外围隔离晶体管。 在晶体管和周围源极/漏极金属层的部分上构图非导电间隔物。

公开(公告)号：WO2016140975A1

公开(公告)日：2016-09-09

申请号：PCT/US2016/020278

申请日：2016-03-01

Applicant: CBRITE INC.

Inventor： SHIEH, Chan-Long ,  FOONG, Fatt ,  YU, Gang ,  WANG, Guangming

IPC: H01L21/00

CPC classification number: H01L27/1266 ,  H01L27/1222 ,  H01L27/1225 ,  H01L29/78669 ,  H01L29/78678 ,  H01L29/7869 ,  H01L51/003 ,  H01L51/0541 ,  H01L51/0545 ,  H01L51/56 ,  H01L2227/323 ,  H01L2227/326

Abstract: The process of fabricating a flexible TFT back-panel includes depositing etch stop material on a glass support. A matrix of contact pads, gate electrodes and gate dielectric are deposited overlying the etch stop material. Vias are formed through the dielectric in communication with each pad. A matrix of TFTs is formed by depositing and patterning metal oxide semiconductor material to form an active layer of each TFT overlying the gate electrode. Source/drain metal is deposited on the active layer and in the vias in contact with the pads, the source/drain metal defining source/drain terminals of each TFT. Passivation material is deposited in overlying relationship to the TFTs. A color filter layer is formed on the passivation material and a flexible plastic carrier is affixed to the color filter. The glass support member and the etch stop material are then etched away to expose a surface of each of the pads.

Abstract translation: 制造柔性TFT后面板的过程包括在玻璃支架上沉积蚀刻停止材料。 接触焊盘，栅极电极和栅极电介质的矩阵沉积在蚀刻停止材料上。 通过与每个焊盘连通的电介质形成通孔。 通过沉积和图案化金属氧化物半导体材料形成TFT的矩阵，以形成覆盖栅电极的每个TFT的有源层。 源极/漏极金属沉积在有源层上，并且在与焊盘接触的通孔中，源极/漏极金属限定每个TFT的源极/漏极端子。 钝化材料以与TFT相重叠的关系沉积。 在钝化材料上形成滤色器层，并将柔性塑料载体固定在滤色器上。 然后将玻璃支撑构件和蚀刻停止材料蚀刻掉以暴露每个焊盘的表面。

公开(公告)号：WO2014099590A1

公开(公告)日：2014-06-26

申请号：PCT/US2013/074607

申请日：2013-12-12

Applicant: CBRITE INC.

Inventor： SHIEH, Chan-Long ,  FOONG, Fatt ,  MUSOLF, Juergen ,  YU, Gang

IPC: H01L21/00

CPC classification number: H01L29/7869 ,  H01L29/66969 ,  H01L29/78696

Abstract: A metal oxide thin film transistor includes a metal oxide semiconductor channel with the metal oxide semiconductor having a conduction band with a first energy level. The transistor further includes a layer of passivation material covering at least a portion of the metal oxide semiconductor channel. The passivation material has a conduction band with a second energy level equal to, or less than 0.5 eV above the first energy level.

Abstract translation: 金属氧化物薄膜晶体管包括金属氧化物半导体沟道，金属氧化物半导体具有具有第一能级的导带。 晶体管还包括覆盖金属氧化物半导体沟道的至少一部分的钝化材料层。 钝化材料具有等于或小于第一能级高于0.5eV的第二能级的导带。