公开(公告)号：WO2021167822A1

公开(公告)日：2021-08-26

申请号：PCT/US2021/017393

申请日：2021-02-10

Applicant: CREE, INC.

Inventor： KOMPOSCH, Alexander ,  WARD, Simon ,  CHIDURALA, Madhu

IPC: H01L23/498 ,  H01L21/58 ,  H01L23/02 ,  H01L23/538 ,  H01L27/15 ,  H01L33/62

Abstract: A device includes: a surface mount device carrier configured to be mounted to a metal submount of a transistor package, said surface mount device carrier includes an insulating substrate includes a top surface and a bottom surface and a first pad and a second pad arranged on a top surface of said surface mount device carrier; at least one surface mount device includes a first terminal and a second terminal, said first terminal of said surface mount device mounted to said first pad and said second terminal mounted to said second pad; and at least one of the first terminal and the second terminal being configured to be isolated from the metal submount by said insulating substrate, where at least one of the first pad and the second pad are configured as wire bond pads.

公开(公告)号：WO2020236585A1

公开(公告)日：2020-11-26

申请号：PCT/US2020/033124

申请日：2020-05-15

Applicant: CREE, INC.

Inventor： CHIDURALA, Madhu ,  MARBELL, Marvin ,  WARD, Simon

IPC: H01L23/66 ,  H03F1/02 ,  H03F3/195 ,  H03F3/213 ,  H03F3/24

Abstract: In integrating RF power amplifier circuits on a package, at least one bias voltage is coupled to at least one amplifier circuit on the package via two or more pins/connectors. In particular, at least one of a gate and drain bias voltage is coupled to one or more amplifier circuits via at least two pins/connectors. In some embodiments, the two or more bias voltage pins/connectors are connected together on the package, placing the pins/connectors in parallel, which reduces an inductance associated with the pins/connectors. In some embodiments, at least of the two pins/connectors connected to the same bias voltage are disposed on either side of an RF signal pin/conductor, simplifying the routing of signals on the package, affording greater flexibility of placement and routing on the package.

公开(公告)号：WO2021202074A1

公开(公告)日：2021-10-07

申请号：PCT/US2021/021845

申请日：2021-03-11

Applicant: CREE, INC.

Inventor： WILSON, Richard ,  CHIDURALA, Madhu

IPC: H01L23/66 ,  H03F1/56 ,  H01L2223/6611 ,  H01L2223/6655 ,  H01L2223/6672 ,  H01L2223/6683 ,  H01L2224/08145 ,  H01L2224/08225 ,  H01L2224/16145 ,  H01L2224/48137 ,  H01L2224/48157 ,  H01L2224/48195 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L23/04 ,  H01L23/057 ,  H01L23/4334 ,  H01L23/49531 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/08 ,  H01L24/48 ,  H01L25/18 ,  H01L2924/19107

Abstract: A multi-level radio frequency (RF) integrated circuit component includes an upper level including at least one inductor, and a lower level including at least one conductive element that provides electrical connection to the at least one inductor. The lower level separates the at least one inductor from a lower surface that is configured to be attached to a conductive pad. Related integrated circuit device packages are also discussed.

公开(公告)号：WO2021257853A1

公开(公告)日：2021-12-23

申请号：PCT/US2021/037864

申请日：2021-06-17

Applicant: CREE, INC.

Inventor： CHIDURALA, Madhu ,  MARBELL, Marvin ,  THULIN, Niklas

IPC: H03F1/02 ,  H03F3/19 ,  H03F3/24 ,  H03F1/0288 ,  H03F1/565 ,  H03F2200/451 ,  H03F2200/555 ,  H03F3/195 ,  H03F3/245

Abstract: An electronic package houses one or more RF amplifiers (18, 18a, 18b). At least one of an input or output impedance matching network (16, 16a, 16b, 20, 20a, 20b) integrated on the package and electrically coupled to the gate or drain bias voltage connection, respectively, of an RF amplifier (18, 18a, 18b), includes a multi-stage decoupling network. Each multi-stage decoupling network includes two or more decoupling stages. Each decoupling stage of the multi-stage decoupling network includes a resistance, inductance, and capacitance, and is configured to reduce impedance seen by the RF amplifier (18, 18a, 18b) at a different frequency below an operating band of the amplifier circuit. Bias voltage connections to the impedance matching networks (16, 16a, 16b, 20, 20a, 20b) may be shared, and may be connected anywhere along the multi-stage decoupling network.

公开(公告)号：WO2020191137A1

公开(公告)日：2020-09-24

申请号：PCT/US2020/023526

申请日：2020-03-19

Applicant: CREE, INC.

Inventor： JANG, Haedong ,  ARISTUD, Sonoko ,  MARBELL, Marvin ,  CHIDURALA, Madhu

IPC: H03F1/02 ,  H03F3/195 ,  H03F3/24 ,  H03F1/56

Abstract: In an asymmetric Doherty amplifier circuit (36), one or more shunt reactive components are added to at least one side of an impedance inverter (38) connecting the amplifier outputs, to reduce a capacitance imbalance between the two amplifiers (14a, 14b) caused by their different parasitic capacitances (C DS1 , C DS2 ). This enables the (adjusted) parasitic capacitances to be incorporated into a quarter-wavelength transmission line, having a 90-degree phase shift, for the impedance inverter (38). In one embodiment, a shunt inductance (L SH ) is connected between the impedance inverter, on the side of the larger amplifier (14b), and RF signal ground. The inductance (L SH1 ) is sized to resonate away substantially the excess parasitic capacitance of the larger amplifier (14b). In another embodiment, a shunt capacitor (C SH ) is connected on the side of the smaller amplifier (14a), thus raising its total capacitance to substantially equal the parasitic capacitance of the larger amplifier (14b). In other embodiments shunt inductances (LSH, LSH1, LSH2) and/or capacitors (C SH , C SH1 , C SH2 ) may be added to one or both amplifiers (14a, 14b), and sized to effectively control a characteristic impedance of the impedance inverter (38).