公开(公告)号：WO2023274958A1

公开(公告)日：2023-01-05

申请号：PCT/EP2022/067562

申请日：2022-06-27

申请人： VITESCO TECHNOLOGIES GERMANY GMBH

发明人： HÖVERMANN, Markus ,  HABER, Michael ,  KRASSELT, Peter ,  METZLER, Martin ,  EHRMANN, Martin

IPC分类号： H01L25/07 ,  H01L25/18 ,  H01L23/48 ,  H01L23/00 ,  H02M7/00 ,  H01L2224/04034 ,  H01L2224/04042 ,  H01L2224/291 ,  H01L2224/32225 ,  H01L2224/40227 ,  H01L2224/73221 ,  H01L2224/8384 ,  H01L24/08 ,  H01L24/40 ,  H01L25/072 ,  H02M1/327 ,  H02M1/348 ,  H02M7/003 ,  H02M7/5387

摘要： Ein Leistungshalbbrückenmodul (LM) weist eine Leiterplatte (LP) mit einem ersten Längsabschnitt (AB1), in dem zwei Stromanschlussschienen (SS1, SS4) teilweise übereinander angeordnet sind. Diese bilden Kontaktflächen (KF11, KF4) zur externen Verbindung aus. Ein erster der Stromanschlussschienen (SS1) erstreckt sich weiter in einen zweiten Längsabschnitt (AB2). In diesem hat die Leiterplatte (LP) mindestens eine Ausnehmung (AS1). Im zweiten Längsabschnitt (AB2) weist die erste Stromanschlussschiene (SS1) Kontaktflächen (KF12, 13) in einem Randbereich auf, der die Ausnehmung (AS1) zumindest an einer Seite der Ausnehmung umgibt. Im weiteren Verlauf des zweiten Längsabschnitts (AB2) ist eine zusätzliche Stromanschlussschiene (SS5) vorgesehen, der bis sich zu dem Ende erstreckt, das dem Ende entgegengesetzt ist, zu dem sich die zwei Stromanschlussschienen (SS1, SS4) hin erstrecken. Ein Halbleiter-Träger (HT) weist auf einer Seite zwei nebeneinanderliegende Stromanschlussschiene (SS2, SS3) auf. Auf diesen ist jeweils ein Halbleiterschalter montiert, etwa durch Löten oder Sintern. Die Halbleiterschalter ragen in die Ausnehmung (AS1) der Leiterplatte (LP) hinein, so dass eine oberflächenbezogene Verbindung eine oberseitige Verbindungsfläche eines der Halbleiterschalter (HS2) mit der Kontaktfläche (KF12) verbindet, etwa eine Bonding-Verbindung. Auch der andere Halbleiterschalter (HS1) hat eine oberseitige Verbindungsfläche. Diese ist durch eine weitere oberflächenbezogene Verbindung mit dem Stromträger verbunden, auf dem der erstgenannte Halbleiterschalter (HS2) angeordnet ist. Das Leistungshalbbrückenmodul kann zum Aufbau eines Inverters verwendet werden. Ferner wird ein zugehöriges Herstellungsverfahren beschrieben.

公开(公告)号：WO2022005846A1

公开(公告)日：2022-01-06

申请号：PCT/US2021/038696

申请日：2021-06-23

申请人： INVENSAS BONDING TECHNOLOGIES, INC.

发明人： HABA, Belgacem

IPC分类号： H01L23/16 ,  H01L23/495 ,  H01L21/56 ,  H01L23/31 ,  H01L21/561 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/78 ,  H01L2221/68327 ,  H01L2223/54426 ,  H01L2224/08145 ,  H01L2224/80006 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L23/3121 ,  H01L23/3737 ,  H01L23/481 ,  H01L23/544 ,  H01L23/562 ,  H01L24/08 ,  H01L24/80 ,  H01L24/96 ,  H01L25/0657

摘要： In one embodiment, an integrated device package is disclosed. The integrated device package can comprise a carrier an a molding compound over a portion of an upper surface of the carrier. The integrated device package can comprise an integrated device die mounted to the carrier and at least partially embedded in the molding compound, the integrated device die comprising active circuitry. The integrated device package can comprise a stress compensation element mounted to the carrier and at least partially embedded in the molding compound, the stress compensation element spaced apart from the integrated device die, the stress compensation element comprising a dummy stress compensation element devoid of active circuitry. At least one of the stress compensation element and the integrated device die can be directly bonded to the carrier without an adhesive.

公开(公告)号：WO2021259477A1

公开(公告)日：2021-12-30

申请号：PCT/EP2020/067772

申请日：2020-06-25

申请人： HUAWEI TECHNOLOGIES CO., LTD. ,  BADAROGLU, Mustafa

发明人： BADAROGLU, Mustafa

IPC分类号： H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L2224/03845 ,  H01L2224/04105 ,  H01L2224/05609 ,  H01L2224/05611 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/08145 ,  H01L2224/08147 ,  H01L2224/80006 ,  H01L2224/80013 ,  H01L2224/80047 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L2224/94 ,  H01L2224/96 ,  H01L2225/06593 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L24/94 ,  H01L24/96 ,  H01L25/0657 ,  H01L25/50

摘要： A method of stacking semiconductor components, to obtain a semiconductor wafer assembly, and for forming a semiconductor die assembly therefrom, is provided. The method comprises providing a first wafer comprising at least a first and a second die in a first and a second position, respectively; providing at least a third and a fourth die, to be stacked on the first and the second die, respectively; placing the third and fourth die on a carrier wafer in positions matching at least a part of the first and second position, respectively; applying insulating material on the carrier wafer outside of the third and the fourth dies; and placing the carrier wafer on the first wafer to obtain a first die stack of the first and third dies and a second die stack of the second and fourth dies, causing bonding of the first and third dies and the second and fourth dies, respectively.

公开(公告)号：WO2021138794A1

公开(公告)日：2021-07-15

申请号：PCT/CN2020/070614

申请日：2020-01-07

申请人： YANGTZE MEMORY TECHNOLOGIES CO., LTD.

发明人： HE, Jialan

IPC分类号： H01L21/98 ,  H01L21/78 ,  H01L25/18 ,  H01L2224/08145 ,  H01L2224/80006 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06524 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/50 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/14511

摘要： A method includes providing a structure including a carrier wafer, and a first device wafer with an adhesion layer between the carrier wafer and the first device wafer; and forming a plurality of first ablation structures in the structure, each of the plurality of first ablation structures extending through the first device wafer, the adhesion layer and a portion of the carrier wafer. Each of the plurality of first ablation structures has a portion inside the carrier wafer with a depth no greater than one half of a thickness of the carrier wafer. The first device wafer includes a plurality of first dies, each pair of adjacent first dies being separated by one of the plurality of first ablation structures. The plurality of first ablation structures are formed by either laser grooving or mechanical sawing.

公开(公告)号：WO2023277310A1

公开(公告)日：2023-01-05

申请号：PCT/KR2022/004856

申请日：2022-04-05

申请人： 삼성전자주식회사

发明人： 김명희 ,  박태순

IPC分类号： H01L33/20 ,  H01L33/38 ,  H01L33/62 ,  H01L33/48 ,  H01L2224/05553 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/08147 ,  H01L2224/80136 ,  H01L2224/80203 ,  H01L2224/80805 ,  H01L2224/95101 ,  H01L2224/95136 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L24/95 ,  H01L25/0753 ,  H01L25/167 ,  H01L2924/12041 ,  H01L33/24 ,  H01L33/325

摘要： 무기 발광 소자, 디스플레이 모듈 및 디스플레이 모듈의 제조 방법이 개시된다. 개시된 무기 발광 소자는, 제1 반도체층과, 4변으로 이루어진 발광면을 가지는 제2 반도체층과, 제1 및 제2 반도체층 사이에 배치된 활성층과, 제1 반도체층과 연결된 제1 전극과, 제2 반도체층과 연결된 제2 전극을 포함하며, 상기 발광면은 사다리꼴이며, 상기 발광면의 2개의 마주하는 변들이 대칭일 수 있다.

公开(公告)号：WO2022271241A1

公开(公告)日：2022-12-29

申请号：PCT/US2022/021880

申请日：2022-03-25

申请人： INTEL CORPORATION

发明人： WAIDHAS, Bernd ,  HANNA, Carlton ,  MOREIN, Stephen ,  KESER, Lizbeth ,  SEIDEMANN, Georg

IPC分类号： H01L25/065 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L25/18 ,  H01L23/36 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/08225 ,  H01L2224/24137 ,  H01L23/3675 ,  H01L23/481 ,  H01L23/5389 ,  H01L24/05 ,  H01L24/06 ,  H01L24/08 ,  H01L24/24 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/16 ,  H01L25/50 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19106 ,  H05K1/181

摘要： Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate including a first conductive pathway electrically coupled to a power source; a mold material on the package substrate including a first microelectronic component embedded in the mold material, a second microelectronic component embedded in the mold material, and a TMV, between the first and second microelectronic components, the TMV electrically coupled to the first conductive pathway; a redistribution layer (RDL) on the mold material including a second conductive pathway electrically coupled to the TMV; and a third microelectronic component on the RDL and electrically coupled to the second conductive pathway, wherein the second conductive pathway electrically couples the TMV, the first microelectronic component, and the third microelectronic component.

公开(公告)号：WO2022212594A1

公开(公告)日：2022-10-06

申请号：PCT/US2022/022673

申请日：2022-03-30

申请人： INVENSAS BONDING TECHNOLOGIES, INC.

发明人： GAO, Guilian ,  FOUNTAIN, Gaius, Gillman, Jr.

IPC分类号： H01L21/18 ,  H01L21/683 ,  H01L21/306 ,  H01L2224/08145 ,  H01L2224/80006 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L24/08 ,  H01L24/80

摘要： A method of processing a semiconductor element is disclosed. The method can include providing the semiconductor element that has a first nonconductive material. The first nonconductive material is disposed on a device portion of the semiconductor element. The method can include providing a transparent carrier. The method can include providing an intervening structure that has a second nonconductive material, a photolysis layer, and an opaque layer stacked together. The method can include forming a bonded structure such that the second nonconductive material is directly bonded to the first nonconductive material or to the transparent carrier. The intervening structure is disposed between the semiconductor element and the transparent carrier. The method can include decoupling the transparent carrier from the semiconductor element by exposing the photolysis layer to light through the transparent carrier such that the light decomposes the photolysis layer.

公开(公告)号：WO2021243686A1

公开(公告)日：2021-12-09

申请号：PCT/CN2020/094582

申请日：2020-06-05

申请人： YANGTZE MEMORY TECHNOLOGIES CO., LTD.

发明人： WANG, Di ,  ZHOU, Wenxi ,  XIA, Zhiliang ,  YANG, Yonggang ,  ZHANG, Kun ,  ZHANG, Hao ,  AI, Yiming

IPC分类号： H01L27/11551 ,  H01L2224/0231 ,  H01L2224/02331 ,  H01L2224/02333 ,  H01L2224/02373 ,  H01L2224/02381 ,  H01L23/4824 ,  H01L24/03 ,  H01L24/08 ,  H01L24/11 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582

摘要： Aspects of the disclosure provide a semiconductor device and a method for fabricating the same. The method for fabricating the semiconductor device can include forming a stack of alternating first insulating layers and first sacrificial layers over a semiconductor substrate, and forming a staircase in the stack having a plurality of steps, with at least a first step of the staircase including a first sacrificial layer of the first sacrificial layers over a first insulating layer of the first insulating layers. Further, the method can include forming a recess in the first sacrificial layer, forming a second sacrificial layer in the recess, and replacing a portion of the first sacrificial layer and the second sacrificial layer with a conductive material that forms a contact pad.

公开(公告)号：WO2021145916A1

公开(公告)日：2021-07-22

申请号：PCT/US2020/035612

申请日：2020-06-01

申请人： SANDISK TECHNOLOGIES LLC

发明人： WU, Chen ,  RABKIN, Peter ,  HIGASHITANI, Masaaki

IPC分类号： H05K3/04 ,  H01L29/40 ,  H05K3/10 ,  H01L23/532 ,  H01L21/768 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03462 ,  H01L2224/03614 ,  H01L2224/03616 ,  H01L2224/03622 ,  H01L2224/05557 ,  H01L2224/05567 ,  H01L2224/0557 ,  H01L2224/05583 ,  H01L2224/05647 ,  H01L2224/08147 ,  H01L2224/80001 ,  H01L24/03 ,  H01L24/05 ,  H01L24/08 ,  H01L24/89 ,  H01L25/18 ,  H01L25/50 ,  H01L27/11526 ,  H01L27/11556 ,  H01L2924/1431 ,  H01L2924/14511

摘要： A semiconductor die includes a first pad-level dielectric layer embedding first bonding pads and located over a first substrate. Each of the first bonding pads is located within a respective pad cavity in the first pad-level dielectric layer. Each of the first bonding pads includes a first metallic liner containing a first metallic liner material and contacting a sidewall of the respective pad cavity, a first metallic fill material portion embedded in the first metallic liner, and a metallic electromigration barrier layer contacting the first metallic fill material portion and adjoined to the first metallic liner.

公开(公告)号：WO2021141660A1

公开(公告)日：2021-07-15

申请号：PCT/US2020/059326

申请日：2020-11-06

申请人： RAYTHEON COMPANY

发明人： GETTY, Jonathan ,  LOFGREEN, Daniel D. ,  MILLER, Alexandra V.

IPC分类号： H01L23/00 ,  H01L2224/05567 ,  H01L2224/05571 ,  H01L2224/05609 ,  H01L2224/05655 ,  H01L2224/0807 ,  H01L2224/08147 ,  H01L2224/80211 ,  H01L2224/80345 ,  H01L2224/80359 ,  H01L2224/80815 ,  H01L2224/80896 ,  H01L2224/83209 ,  H01L2224/83409 ,  H01L2224/83896 ,  H01L24/05 ,  H01L24/08 ,  H01L24/27 ,  H01L24/30 ,  H01L24/80 ,  H01L2924/14

摘要： A direct bond hybridization (DBH) method is provided. The DBH method includes preparing a first underlying layer, a first contact layer disposed on the first underlying layer and a first contact electrically communicative with the first underlying layer and protruding through the first contact layer, preparing a second underlying layer, a second contact electrically communicative with the second underlying layer and formed of softer material than the first contact and a second contact layer disposed on the second underlying layer and defining an aperture about the second contact and a moat at least partially surrounding the second contact and bonding the first and second contact layers whereby the first contact contacts the second contact such that the second contact deforms and expands into the moat.