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公开(公告)号：WO2021041257A1
公开(公告)日：2021-03-04
申请号：PCT/US2020/047512
申请日：2020-08-21
Applicant: CRYPTOGRAPHY RESEARCH, INC.
Inventor： BEST, Scott C.
Abstract: A resistor mesh with distributed sensing points is provided in a security chip as an anti-tamper shield. An analog multiplexing circuit is configured to receive a pair of digital selection values created by an algorithm processing circuit, and produce a respective differential voltage formed by a pair of voltages obtained at a pair of selected sensing points within the resistor mesh corresponding to the pair of digital selection values. Each differential voltage is converted into a corresponding digital output value. An algorithm processing circuit is configured to receive a respective digital output value associated with each pair of digital selection values and derive a binary value based on a subset of the digital output values, wherein the binary value is unique to the security chip.
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公开(公告)号：WO2019055307A1
公开(公告)日：2019-03-21
申请号：PCT/US2018/049939
申请日：2018-09-07
Applicant: CRYPTOGRAPHY RESEARCH, INC.
Inventor： BEST, Scott C. , LI, Ming
IPC: H01L23/00
Abstract: The embodiments herein are directed to technologies for backside security meshes of semiconductor packages. One package includes a substrate having a first interconnect terminal of a first type and a second interconnect terminal of a second type. The package also includes a first security mesh structure disposed on a first side of an integrated circuit die and a conductive path coupled between the first interconnect terminal and the second interconnect terminal. The first security mesh structure is coupled to the first interconnect terminal and the second interconnect terminal being coupled to a terminal on a second side of the integrated circuit die.
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Patent Agency Ranking
公开(公告)号：WO2017087552A1
公开(公告)日：2017-05-26
申请号：PCT/US2016/062331
申请日：2016-11-16
Applicant: CRYPTOGRAPHY RESEARCH, INC.
Inventor： WITTENAUER, Joel Patrick , BEST, Scott C. , KOCHER, Paul Carl
IPC: H04L9/28
CPC classification number: H04L9/3271
Abstract: A table key capable of decrypting a first table from a plurality of encrypted tables may be received. Each of the encrypted tables may include at least one pair of values corresponding to a challenge value and a response value. A request to authenticate a secondary device may be received and in response to the request to authenticate the secondary device, a challenge value obtained by using the table key to decrypt an entry in the first table may be transmitted to the secondary device. A second challenge value may be transmitted to the secondary device and a cryptographic proof may be received from the secondary device. The validity of the cryptographic proof received from the secondary device may be authenticated based on the second challenge value and the response value obtained by using the table key to decrypt the entry in the first table.
Abstract translation: 可以接收能够从多个加密表格中解密第一表格的表格密钥。 每个加密表可以包括对应于挑战值和响应值的至少一对值。 可以接收认证次级设备的请求，并且响应于认证次级设备的请求，可以将通过使用表密钥解密第一表中的条目而获得的质询值发送到次级设备。 第二挑战值可以被发送到辅助设备并且可以从辅助设备接收密码证据。 可以基于第二挑战值和通过使用表密钥来解密第一表中的条目而获得的响应值来认证从次设备接收的密码证明的有效性。
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公开(公告)号：WO2016099724A1
公开(公告)日：2016-06-23
申请号：PCT/US2015/060412
申请日：2015-11-12
Applicant: CRYPTOGRAPHY RESEARCH, INC.
Inventor： BEST, Scott C.
IPC: G06F7/58
Abstract: The embodiments described herein describe technologies of self-timed, digital chaotic pattern generators. The self-timed, digital chaotic pattern generators (CGs) can be used to form an N-bit, self-timed, random number generator (RNG) to generate a random digital value. The entropy of the random digital value is based on both the asynchronous, self-timed chaotic mixings, as well as the metastability of internal latches of the N-bit, self-timed, RNG.
Abstract translation: 本文描述的实施例描述了自定时数字混沌模式发生器的技术。 自定时数字混沌模式发生器（CG）可用于形成一个N位，自定时随机数发生器（RNG），以生成随机数字值。 随机数字值的熵基于异步，自定时混沌混合以及N位，自定时RNG的内部锁存器的亚稳态。
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公开(公告)号：WO2021118816A1
公开(公告)日：2021-06-17
申请号：PCT/US2020/062553
申请日：2020-11-30
Applicant: CRYPTOGRAPHY RESEARCH, INC.
Inventor： HUTTER, Michael , HANDSCHUH, Helena , BEST, Scott C.
Abstract: Hardware masking may be used as a countermeasure to make power analysis attacks more difficult. Masking attempts to decouple the secret and/or processed values of a cryptographic algorithm from its intermediate values. One method of masking probabilistically splits each bit of a computation into multiple shares. Mask-share domains (i.e., the wires and gates that perform a computation on a share) are physically spaced to reduce coupling between mask-share domains. The mask-share domains may be connected to the same power supply network. The physical distance between mask-share domains along the power-supply network may be selected to reduce coupling between mask-share domains that may occur via the power supply network. The mask-share domains may each be connected to different on-chip power supply networks.
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公开(公告)号：WO2020106339A3
公开(公告)日：2020-05-28
申请号：PCT/US2019/046631
申请日：2019-08-15
Applicant: CRYPTOGRAPHY RESEARCH, INC.
Inventor： BEST, Scott C.
IPC: G06F21/75 , H03K19/177
Abstract: Described are technologies of all-digital camouflage circuits. The camouflage circuit can include a first chain of inverters, synthesized with a first standard cell with a first transistor threshold, and a second chain of inverters, synthesized with a second standard cell with a second transistor threshold that is different than the first transistor threshold. A first flip-flop receives a first output of the first chain as a data input and a second output of the second chain as a clock input. A second flip-flop receives the second output as a data input and the first output of the first chain as a clock input. Given the different transistor thresholds, one flip-flop always outputs an active signal that corresponds to an input signal applied to the first chain and the second chain. The other flip-flop always output a constant signal, such an always low signal.
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公开(公告)号：WO2020106339A2
公开(公告)日：2020-05-28
申请号：PCT/US2019/046631
申请日：2019-08-15
Applicant: CRYPTOGRAPHY RESEARCH, INC.
Inventor： BEST, Scott C.
IPC: H01L29/72
Abstract: Described are technologies of all-digital camouflage circuits. The camouflage circuit can include a first chain of inverters, synthesized with a first standard cell with a first transistor threshold, and a second chain of inverters, synthesized with a second standard cell with a second transistor threshold that is different than the first transistor threshold. A first flip-flop receives a first output of the first chain as a data input and a second output of the second chain as a clock input. A second flip-flop receives the second output as a data input and the first output of the first chain as a clock input. Given the different transistor thresholds, one flip-flop always outputs an active signal that corresponds to an input signal applied to the first chain and the second chain. The other flip-flop always output a constant signal, such an always low signal.
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