公开(公告)号：WO2022040155A1

公开(公告)日：2022-02-24

申请号：PCT/US2021/046257

申请日：2021-08-17

Applicant: MONOLITHIC POWER SYSTEMS, INC.

Inventor： PALA, Vipindas ,  UPPILI, Sudarsan

IPC: H01L29/66 ,  H01L29/68 ,  H01L29/70 ,  H01L29/72 ,  H01L29/73 ,  H01L29/732

Abstract: Junction field effect transistors (JFETs) and related manufacturing methods are disclosed herein. A disclosed JFET includes a vertical channel region located in a mesa and a first channel control region located on a first side of the mesa. The first channel control region is at least one of a gate region and a first base region. The JEFT also includes a second base region located on a second side of the mesa and extending through the mesa to contact the vertical channel region. The vertical channel can be an implanted vertical channel. The vertical channel can be asymmetrically located in the mesa towards the first side of the mesa.

公开(公告)号：WO2012145130A2

公开(公告)日：2012-10-26

申请号：PCT/US2012/030904

申请日：2012-03-28

Applicant: MICRON TECHNOLOGY, INC. ,  RAMASWAMY, D.V. Nirmal ,  SANDHU, Gurtej S.

Inventor： RAMASWAMY, D.V. Nirmal ,  SANDHU, Gurtej S.

IPC: H01L21/328 ,  H01L29/72

CPC classification number: H01L29/872 ,  G11C11/5678 ,  G11C13/0004 ,  G11C2213/71 ,  H01L27/1021 ,  H01L27/224 ,  H01L27/2409 ,  H01L27/285 ,  H01L29/885 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/146 ,  H01L45/147 ,  H01L45/16

Abstract: Methods, devices, and systems are provided for a select device that can include a semiconductive stack of at least one semiconductive material formed on a first electrode, where the semiconductive stack can have a thickness of about 700 angstroms () or less. Each of the at least one semiconductive material can have an associated band gap of about 4 electron volts (eV) or less and a second electrode can be formed on the semiconductive stack.

Abstract translation: 为选择装置提供方法，装置和系统，所述选择装置可以包括形成在第一电极上的至少一个半导体材料的半导体叠层，其中半导体叠层可以具有约700埃（℃）或更小的厚度。 所述至少一个半导体材料中的每一个可以具有约4电子伏（eV）或更小的相关带隙，并且可以在半导体叠层上形成第二电极。

公开(公告)号：WO2012075905A1

公开(公告)日：2012-06-14

申请号：PCT/CN2011/083300

申请日：2011-12-01

Applicant: CSMC TECHNOLOGIES FAB1 CO., LTD. ,  CSMC TECHNOLOGIES FAB2 CO., LTD. ,  WANG, Le

Inventor： WANG, Le

IPC: H01L29/72 ,  H01L29/735

CPC classification number: H01L29/7393 ,  H01L29/66325

Abstract: An insulated gate bipolar transistor (IGBT) is disclosed. The IGBT includes a substrate containing a substrate layer and an epitaxial layer formed on one side of the substrate layer. The IGBT also includes a well region formed in the epitaxial layer, and a gate region formed over a junction between the well region and the epitaxial layer. Further, the IGBT includes a collector drift region formed in the epitaxial layer, and an emitter drift region formed in the well region. The IGBT also includes a collector formed on the collector drift region, an emitter formed on the emitter drift region, and a gate formed on the gate region. The collector, the emitter, and the gate are arranged at a same side of the substrate layer.

Abstract translation: 公开了一种绝缘栅双极晶体管（IGBT）。 IGBT包括含有衬底层和形成在衬底层的一侧上的外延层的衬底。 IGBT还包括形成在外延层中的阱区和形成在阱区和外延层之间的结上方的栅极区。 此外，IGBT包括形成在外延层中的集电极漂移区和形成在阱区中的发射极漂移区。 IGBT还包括形成在集电极漂移区上的集电极，形成在发射极漂移区上的发射极和形成在栅极区上的栅极。 集电极，发射极和栅极配置在基板层的同一侧。

公开(公告)号：WO2011050161A1

公开(公告)日：2011-04-28

申请号：PCT/US2010/053544

申请日：2010-10-21

Applicant: THE TRUSTEES OF COLUMBIA UNIVERSITY IN THE CITY OF NEW YORK ,  CHEN, Xi

Inventor： CHEN, Xi

IPC: H01L29/72 ,  H01L29/84

CPC classification number: B29C53/02 ,  B81C1/00031 ,  B81C2201/0149

Abstract: Self-assembled buckling patterns of thin films on compliant substrates can be used in micro-fabrication. However, most previous work has been limited to planar substrates, and buckling of films on curved substrates has not been widely explored. With the constraining effect from various types of substrate curvature, numerous new types of buckling morphologies can be derived. The morphologies not only enable true three-dimensional (3D) fabrication of microstructures and microdevices, but also can have important implications for the morphogenesis of quite a few natural and biological systems.

Abstract translation: 柔性衬底上的薄膜的自组装弯曲图案可用于微加工。 然而，大多数以前的工作已经限于平面基板，并且弯曲基板上的膜的屈曲尚未得到广泛的探索。 通过各种基体曲率的约束效应，可得出许多新型的屈曲形态。 形态不仅可以实现三维（3D）微结构和微型器件的制造，而且可以对相当多的自然和生物系统的形态发生具有重要意义。

公开(公告)号：WO2006039669A3

公开(公告)日：2008-06-26

申请号：PCT/US2005035534

申请日：2005-09-30

Applicant: TEXAS INSTRUMENTS INC ,  MEHRAD FREIDOON ,  ROUSE RICHARD ,  CHURCHILL ROBERT B

Inventor： MEHRAD FREIDOON ,  ROUSE RICHARD ,  CHURCHILL ROBERT B

IPC: H01L29/72 ,  H01L21/82 ,  H01L21/8238 ,  H01L23/58 ,  H01L29/00

CPC classification number: H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An e-fuse (200) for an integrated circuit is formed with a reverse P-N junction in the semiconductor body (205) between fuse contacts (235) and below the conductive (for example, silicide) layer (230), so that when the fuse is blown (that is, the conductive layer melts), conduction through the underlying body is prevented.

Abstract translation: 用于集成电路的电熔丝（200）在半导体本体（205）中的熔丝触点（235）之间并且在导电（例如，硅化物）层（230）下方形成有反向PN结，使得当 保险丝熔断（即，导电层熔化），阻止了通过下层体的传导。

公开(公告)号：WO2004100272A1

公开(公告)日：2004-11-18

申请号：PCT/US2003/014386

申请日：2003-04-29

Applicant: MIDWEST RESEARCH INSTITUTE ,  WANG, Qi

Inventor： WANG, Qi

IPC: H01L29/72

CPC classification number: H01L29/868 ,  Y10T428/265

Abstract: A combination of a thin-film µc-Si and a-Si:H containing diode structure characterized by an ultra-high current density that exceeds 1000 A/cm 2 , comprising: a substrate; a bottom metal layer disposed on the substrate; an n-layer of µc-Si deposited the bottom metal layer; an i-layer of µc-Si deposited on the n-layer; a buffer layer of a-Si:H deposited on the i-layer; a p-layer of µc-Si deposited on the buffer layer; and a top metal layer deposited on the p-layer.

Abstract translation: 薄膜μc-Si和a-Si：H二极管结构的组合，其特征在于超高电流密度超过1000A / cm 2，包括：基板; 设置在所述基板上的底部金属层; μc-Si的n层沉积底部金属层; 沉积在n层上的μc-Si的i层; 沉积在i层上的a-Si：H的缓冲层; 沉积在缓冲层上的μc-Si层的p层; 和沉积在p层上的顶层金属层。

公开(公告)号：WO2003015176A1

公开(公告)日：2003-02-20

申请号：PCT/US2002/022655

申请日：2002-07-17

Applicant: ORIOL, INC. ,  YOO, Myung, Cheol

Inventor： YOO, Myung, Cheol

IPC: H01L29/72

CPC classification number: H01L33/0025 ,  H01L25/0753 ,  H01L33/06 ,  H01L33/12 ,  H01L33/22 ,  H01L33/32 ,  H01L33/387 ,  H01L33/405 ,  H01L33/42 ,  H01L33/46 ,  H01L33/483 ,  H01L33/62

Abstract: A light emitting diode includes a transparent substrate (100) and a GaN buffer layer (120) on the transparent substrate. An n-GaN layer (140) is formed on the buffer layer. An active layer is formed on the n-GaN layer. A p-GaN layer is formed on the active layer. A p-electrode is formed on the p-GaN layer and an n-electrode is formed on the N-GaN layer. A reflective layer (200) is formed on a second side of the transparent substrate. Also, a cladding layer of AlGaN is between the p-GaN layer and the active layer (160).

Abstract translation: 发光二极管包括在透明基板上的透明基板（100）和GaN缓冲层（120）。 在缓冲层上形成n-GaN层（140）。 在n-GaN层上形成有源层。 在活性层上形成p-GaN层。 在p-GaN层上形成p电极，在N-GaN层上形成n电极。 反射层（200）形成在透明基板的第二面上。 此外，AlGaN的包覆层在p-GaN层和有源层之间（160）之间。

公开(公告)号：WO99017372A1

公开(公告)日：1999-04-08

申请号：PCT/US1998/018686

申请日：1998-09-08

IPC: H01L29/73 ,  H01L21/331 ,  H01L29/267 ,  H01L29/737 ,  H01L29/72

CPC classification number: H01L29/66242 ,  H01L29/267 ,  H01L29/7378

Abstract: A heterojunction bipolar transistor (20) is provided with a silicon (Si) base region (34) that forms a semiconductor junction with a multilayer emitter (38) having a thin gallium arsenide (GaAs) emitter layer (36) proximate the base region (34) and a distal gallium phosphide emitter layer (40). The GaAs emitter layer (36) is sufficiently thin, preferably less than 200 ANGSTROM , so as to be coherently strained.

Abstract translation: 异质结双极晶体管（20）设置有硅（Si）基区（34），其与具有接近基极区域（GaAs）的薄砷化镓（GaAs）发射极层（36）的多层发射极（38）形成半导体结， 34）和远端磷化镓发射极层（40）。 GaAs发射极层（36）足够薄，优选地小于200，以致相干地变形。

公开(公告)号：WO1997011496A1

公开(公告)日：1997-03-27

申请号：PCT/JP1995001844

申请日：1995-09-18

Applicant: HITACHI, LTD. ,  OOUE, Eiji ,  ONAI, Takahiro ,  WASHIO, Katsuyoshi ,  KIYOTA, Yukihiro ,  KONDO, Masao ,  ODA, Katsuya ,  MASUDA, Toru

Inventor： HITACHI, LTD.

IPC: H01L29/72

CPC classification number: H01L29/66287 ,  H01L29/1004 ,  H01L29/732

Abstract: A low-power ultrahigh-speed bipolar transistor and a circuit using the same are provided to achieve ultrahigh-speed transmission and receiving of a large quantity of signals as well as low-noise operation of a portable wireless device for extended periods of time. A silicon oxide film (115) is inserted under a polycrystalline silicon graft base (113) that connects a base region (114) to a base polycrystalline silicon electrode (110). This makes it possible to lower the base resistance and the base-collector capacitance, and to obtain a low-power transistor that operates at high speeds.

Abstract translation: 提供了一种低功率超高速双极型晶体管和使用该低电压双极晶体管的电路，以实现长时间的超高速传输和接收大量信号以及便携式无线设备的低噪声操作。 将氧化硅膜（115）插入将基极区（114）与基底多晶硅电极（110）连接的多晶硅移植基体（113）的下方。 这使得可以降低基极电阻和基极集电极电容，并获得在高速下工作的低功率晶体管。

公开(公告)号：WO1993022798A1

公开(公告)日：1993-11-11

申请号：PCT/US1993003789

申请日：1993-04-21

Applicant: NORTH CAROLINA STATE UNIVERSITY

Inventor： NORTH CAROLINA STATE UNIVERSITY ,  NANDAKUMAR, Mahalingam ,  BALIGA, Bantval, Jayant

IPC: H01L29/72

CPC classification number: H01L29/7455

Abstract: An inventive thyristor structure includes anode and cathode electrodes, with a diverter electrode being connected to the cathode electrode. A multi-layer body of semiconductor material has a first surface and includes a regenerative portion (110) operatively coupled between the anode and cathode electrodes, with a non-regenerative portion (120) being operatively coupled between the anode and diverter electrodes. The regenerative portion includes adjacent first (170), second (180), third (200) and fourth regions (240) of alternating conductivity type arranged respectively in series between the cathode and anode electrodes, wherein the cathode electrode is in electrical contact with the first region and the anode electrode is in electrical contact with the fourth region.

Abstract translation: 本发明的晶闸管结构包括阳极和阴极电极，转向电极连接到阴极电极。 半导体材料的多层体具有第一表面，并且包括可操作地耦合在阳极和阴极之间的再生部分（110），非再生部分（120）可操作地耦合在阳极和分流器电极之间。 再生部分包括分别串联布置在阴极和阳极电极之间的交替导电类型的相邻的第一（170），第二（180），第三（200）和第四区域（240），其中阴极电极与 第一区域和阳极电极与第四区域电接触。