公开(公告)号：WO2023057795A1

公开(公告)日：2023-04-13

申请号：PCT/IB2021/059200

申请日：2021-10-07

申请人： CESKE VYSOKE UCENI TECHNICKE V PRAZE

发明人： BELOHOUBEK, Jan ,  FISER, Petr ,  SCHMIDT, Jan

IPC分类号： H03K19/00 ,  G06F21/75 ,  H04L9/00 ,  G11C7/24 ,  G06F21/755 ,  G09C1/00 ,  G11C11/412 ,  H03K19/0013 ,  H04L9/003

摘要： The PMOS block (104) is connected between the virtual supply node (102) and output (101). The NMOS block (105) is connected between the virtual ground node (103) and output (101). The input of the balancing inverter chain (200, 300, 400) is connected to the output O (101). The balancing inverter chain is composed of at least one inverter and the output of the chain is the output (Y) of the structure. The static CMOS circuit (100) is supplemented with any combination of the following circuits. The virtual supply node (102) is connected to the supply rail by a serial P-type transistor (111), which gate (G), is connected to the ground rail. The virtual ground node (103) is connected to the ground rail by the serial N-type transistor (112), which gate (G) is connected to the supply rail. The virtual supply node (102) is connected to the output (101) by the complementary P-type transistor (121). The virtual ground node (103) is connected to the output (101) by the N-type complementary transistor (122).

公开(公告)号：WO2023041911A1

公开(公告)日：2023-03-23

申请号：PCT/GB2022/052332

申请日：2022-09-15

申请人： AGILE ANALOG LTD

发明人： RAMSDALE, Tim ,  MUSZYNSKA, Katarzyna

IPC分类号： G06F21/75 ,  G06F1/28 ,  H04L9/00

摘要： An apparatus for detecting an attack on, or degradation of, an electric circuit is disclosed herein. The apparatus comprises a voltage level detector configured to determine whether the voltage level of the electric circuit exceeds a maximum selected threshold value, and to generate a first binary voltage limitation signal having if the voltage level exceeds the maximum selected threshold value. The apparatus also comprises a marginal voltage level detector configured to determine whether the voltage level of the electric circuit exceeds a marginal selected threshold value, the marginal selected threshold value being less than the maximum selected threshold value, and to generate a second binary voltage limitation signal having if the voltage level exceeds the marginal selected threshold value. A safety monitoring system monitors the first and second binary voltage limitation signals and is configured to determine that a possible attack or degradation has taken place based on at least one of the first binary voltage limitation signal and the second binary voltage limitation signal.

公开(公告)号：WO2023030947A1

公开(公告)日：2023-03-09

申请号：PCT/EP2022/073327

申请日：2022-08-22

申请人： NORDIC SEMICONDUCTOR ASA

发明人： HERNES, Bjørnar ,  DEKENS, Berend ,  PRESTEGÅRD, Håkon ,  KOIVURANTA, Hannu

IPC分类号： G06F21/75 ,  G06F21/57

摘要： An integrated-circuit device (1) comprising a non-volatile memory (NVM) (15), a debug port (21), and debug-port control circuitry (17) for controlling access to the integrated- circuit device (1) through the debug port (21). The debug-port control circuitry (17) is configured to read a first bit array and a second bit array from respective predetermined locations in the NVM (15) in a single read cycle. The second bit array is distinct from the first bit array, and at least the second bit array contains a plurality of bits. The debug-port control circuitry (17) is further configured to determine whether the first bit array has a first predetermined bit pattern and whether the second bit array has a pattern other than a second predetermined bit pattern, and to control access through the debug port (21) at least partly in dependence on said determination.

公开(公告)号：WO2022268364A1

公开(公告)日：2022-12-29

申请号：PCT/EP2022/025288

申请日：2022-06-23

申请人： GIESECKE+DEVRIENT MOBILE SECURITY GMBH

发明人： HOFFMANN, Lars

IPC分类号： H04L9/00 ,  G06F21/75 ,  G06F7/72 ,  G06F7/76 ,  H04W12/47 ,  G06F21/755 ,  G06F2207/7233 ,  G06F7/764 ,  G09C1/00 ,  H04L9/003 ,  H04L9/3066

摘要： Die Erfindung schafft ein Verfahren zur Ummaskierung von einer booleschen Maske zu einer arithmetischen Maske bei einem Modulus (2m *p), in dem m eine ganze Zahl größer gleich null ist, und p mindestens einen Primteiler ungleich 2 besitzt, so dass ein Übertrag erzeugt wird, wobei der Übertrag maskiert oder balanciert wird, um ihn gegen Ausspähung zu schützen.

公开(公告)号：WO2022122470A2

公开(公告)日：2022-06-16

申请号：PCT/EP2021/083542

申请日：2021-11-30

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION ,  IBM UNITED KINGDOM LIMITED

发明人： ZHANG, Hongqing ,  HIGBY, Arthur ,  LEWISON, David ,  BUCHLING, Philipp ,  BUNT, Jay ,  BUSBY, James ,  CAMPBELL, Levi

IPC分类号： G06F21/75 ,  G06F21/86 ,  H05K1/02 ,  H01L23/00 ,  F28F13/003 ,  G06F2221/2143 ,  G08B21/18 ,  H01L23/367 ,  H01L23/3733 ,  H01L23/433 ,  H01L23/57 ,  H05K1/0275 ,  H05K2201/0338 ,  H05K2201/0341 ,  H05K2201/09036 ,  H05K2201/09263 ,  H05K2201/09672 ,  H05K2201/10151 ,  H05K2201/10371 ,  H05K3/4647 ,  H05K7/20409 ,  H05K7/20445

摘要： Tamper-respondent assemblies are provided which include a circuit board, an enclosure assembly mounted to the circuit board, and a pressure sensor. The circuit board includes an electronic component, and the enclosure assembly is mounted to the circuit board to enclose the electronic component within a secure volume. The enclosure assembly includes a thermally conductive enclosure with a sealed inner compartment, and a porous heat transfer element within the sealed inner compartment. The porous heat transfer element is sized and located to facilitate conducting heat from the electronic component across the sealed inner compartment of the thermally conductive enclosure. The pressure sensor senses pressure within the sealed inner compartment of the thermally conductive enclosure to facilitate identifying a pressure change indicative of a tamper event.

公开(公告)号：WO2022029443A1

公开(公告)日：2022-02-10

申请号：PCT/GB2021/052034

申请日：2021-08-05

申请人： PUGGED CODE LIMITED

发明人： THORNTON, Jeremy Simon

IPC分类号： G06F21/75 ,  G06F8/41 ,  G06F9/38 ,  H04L9/00 ,  G06F9/4881 ,  H04L9/003

摘要： There are described methods and apparatus for enhancing security when executing a computer algorithm comprising separately executable tasks, each of which produce an electrical signal when executed. The apparatus comprises memory in which at least part of the computer algorithm is stored as at least one pipeline, wherein the at least one pipeline comprising a plurality of separately executable tasks; and a processor. The processor is configured to receive a plurality of inputs to be processed by the computer algorithm; randomise the plurality of separately executable tasks at a pipeline level and/or at a task level; execute the randomised plurality of separately executable tasks, and repeat the randomising and executing steps until the computer algorithm has processed the plurality of inputs. In this way, at each repetition, the electrical signals produced when executing the plurality of separately executable tasks are randomised to enhance security.

公开(公告)号：WO2022015747A1

公开(公告)日：2022-01-20

申请号：PCT/US2021/041456

申请日：2021-07-13

申请人： VULTARA, INC.

发明人： GUO, Yuanbo

IPC分类号： G06F21/55 ,  G06F21/75 ,  G06F21/76 ,  G06F21/577 ,  G06K9/6267

摘要： Threat-modeling of an embedded system includes receiving a design of the embedded system, the design comprising a component; receiving a feature of the component; identifying an asset associated with the feature, where the asset is targetable by an attacker; identifying a threat to the feature based on the asset; obtaining an impact score associated with the threat; and outputting a threat report that includes at least one of a first description of the threat or a second description of a vulnerability, a respective feasibility score, a respective impact score, and a respective risk score.

公开(公告)号：WO2021140574A1

公开(公告)日：2021-07-15

申请号：PCT/JP2020/000196

申请日：2020-01-07

申请人： 三菱電機株式会社

发明人： 中井　綱人

IPC分类号： G06F21/75 ,  G06F21/60 ,  G06N20/00

摘要： 演算手順変更部（１００）は、機械学習により値が調整される学習パラメータを用いる演算を実行する演算実行タイミングが到来する度に、不規則に、演算手順を、変更前の演算手順にて演算を実行して得られる演算結果と同一の演算結果が得られる変更前の演算手順とは異なる演算手順に変更する。演算実行部（１０１）は、演算実行タイミングが到来する度に、演算手順変更部（１００）による変更後の演算手順にて学習パラメータを用いた演算を実行する。

公开(公告)号：WO2021122907A1

公开(公告)日：2021-06-24

申请号：PCT/EP2020/086662

申请日：2020-12-17

申请人： THALES DIS FRANCE SA ,  THALES DIS DESIGN SERVICES SAS

发明人： LOUBET MOUNDI, Philippe ,  NAURA, David ,  COULON, Jean Roch

IPC分类号： G06F21/75 ,  G06F12/14 ,  G06F21/79 ,  G11C5/14 ,  G11C7/24 ,  G06F12/1441 ,  G06F21/755 ,  G11C5/145

摘要： The present invention relates to a method for executing a security related process comprising at least a first operation and a subsequent programming operation of a memory area in a first memory row of a first memory of a system and using as input security data stored in said second memory of said system, wherein said first memory is a non-volatile memory and said system comprises a first memory charge pump, said method comprising, when the execution of said security related process is triggered: - opening (S2) the first memory row - charging (S3) said first memory charge pump, - performing (S4) said first operations of the security related process, based on said security data from the second memory, - performing (S5) said programming operation of said memory area in said opened first memory row using said charged charge pump..

公开(公告)号：WO2021074595A1

公开(公告)日：2021-04-22

申请号：PCT/GB2020/052493

申请日：2020-10-08

申请人： ARM LIMITED

发明人： WEINER, Michael ,  GOLOMBEK, Oded ,  YELLIN, David

IPC分类号： G06F21/55 ,  G06F21/75 ,  H04L9/00

摘要： A method for obfuscation of operations using minimal additional hardware is presented herein. The method can begin by executing a first iteration of a set of computations, the execution of the set of computations resulting in a first iteration output. The method can continue by executing a second iteration of the set of computations, wherein the second execution is distinct from the first iteration but should satisfy a matching condition. The distinction can be a rearrangement of sub-operations, insertion of dummy sub-operations, or a combination of the two. After the iterations are complete, the iteration outputs can be compared. If the comparison of the first iteration output and the second iteration output satisfy the matching condition, the process result can be output. If the matching condition is not satisfied, an error detected signal can be output.