公开(公告)号：WO2016048318A1

公开(公告)日：2016-03-31

申请号：PCT/US2014/057364

申请日：2014-09-25

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： BUCHANAN, Brent ,  SHARMA, Amit S ,  GIBSON, Gary ,  ORDENTLICH, Erik ,  MURALIMANOHAR, Naveen

IPC: G11C8/10

CPC classification number: G11C8/10 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028

Abstract: Example implementations disclosed herein can be used to decode memory elements in a crosspoint array. In one example implementation, a drain voltage is applied to a drain terminal of a field effect transistor switch for a selected row in the crosspoint array associated with the selected memory element. A bulk terminal of the field effect transistor switch for the selected row can be biased with a well voltage that is independent of the drain, source, or substrate voltages. In such examples, the gate terminal of the field effect transistor switch for the selected row can be driven with a gate voltage comprising the drain voltage and the well voltage. The drain voltage, the well voltage, and the gate voltage are selected to cause the field effect transistor switch for the selected row to operate as an ohmic switch.

Abstract translation: 本文公开的示例实现可以用于解码交叉点阵列中的存储器元件。 在一个示例实现中，漏极电压被施加到与所选存储器元件相关联的交叉点阵列中的所选行的场效应晶体管开关的漏极端子。 用于所选行的场效应晶体管开关的体积端子可以利用独立于漏极，源极或衬底电压的阱电压来偏置。 在这种示例中，用于所选行的场效应晶体管开关的栅极端子可以由包括漏极电压和阱电压的栅极电压驱动。 选择漏极电压，阱电压和栅极电压，使所选行的场效应晶体管开关作为欧姆开关工作。

公开(公告)号：WO2017048293A1

公开(公告)日：2017-03-23

申请号：PCT/US2015/051062

申请日：2015-09-18

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： MURALIMANOHAR, Naveen ,  SHARMA, Amit S ,  BUCHANAN, Brent

IPC: G11C13/00

CPC classification number: G11C13/0059 ,  G11C11/56 ,  G11C11/5614 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0002 ,  G11C13/004 ,  G11C27/024 ,  G11C2013/0045 ,  G11C2013/0054 ,  G11C2211/5641

Abstract: An example device in accordance with an aspect of the present disclosure includes a plurality of first sense circuits of a first type and at least one second sense circuit of a second type. The first sense circuits are to perform first-level sensing of memory elements of a crossbar memory array based on reads that are high-confidence. The second sense circuit is to perform second-level sensing.

Abstract translation: 根据本公开的一个方面的示例性装置包括第一类型的多个第一感测电路和第二类型的至少一个第二感测电路。 第一感测电路是基于高可信度的读取来执行交叉开关存储器阵列的存储器元件的一级感测。 第二感测电路是进行二级感测。