公开(公告)号：WO2019147325A1

公开(公告)日：2019-08-01

申请号：PCT/US2018/060834

申请日：2018-11-13

Applicant: HRL LABORATORIES, LLC

Inventor： PATTERSON, Pamela R. ,  SARKISSIAN, Raymond ,  HUANG, Biqin ,  SAYYAH, Keyvan, R. ,  EFIMOV, Oleg M.

IPC: G02B6/122 ,  G02B6/14 ,  G02B6/12

Abstract: A method of manufacturing an optical waveguide includes: aligning a silicon on insulator wafer and a target substrate, the target substrate including a benzocyclobutene layer; bonding a silicon layer of the silicon on insulator wafer with the benzocyclobutene layer of the target substrate by using heat and pressure; and removing the silicon on insulator wafer such that the silicon layer remains on the benzocyclobutene layer.

公开(公告)号：WO2016168376A1

公开(公告)日：2016-10-20

申请号：PCT/US2016/027384

申请日：2016-04-13

Applicant: HRL LABORATORIES, LLC

Inventor： HUANG, Biqin ,  ROPER, Christopher S. ,  HUSSAIN, Tahir

IPC: G01N27/07 ,  G01N27/414 ,  H01L29/744

CPC classification number: H01J1/308 ,  H01J1/304 ,  H01J9/025 ,  H01J21/10

Abstract: A semiconductor power handling device, includes a cathode pillar, a gate surrounding the cathode pillar, and an anode spaced from the cathode by a nano-vacuum gap. An array of semiconductor power handling devices, each comprises a cathode pillar, a gate surrounding the cathode pillar, and an anode spaced from the cathode pillar by a nano-vacuum gap. The semiconductor power handling devices can be arranged as rows and columns and can be interconnected to meet the requirements of various applications. The array of power handling devices can be fabricated on a single substrate.

Abstract translation: 一种半导体功率处理装置，包括阴极柱，围绕阴极柱的栅极和通过纳米真空间隙与阴极隔开的阳极。 一组半导体功率处理装置，每个包括阴极柱，围绕阴极柱的栅极和通过纳米真空间隙与阴极柱隔开的阳极。 半导体功率处理装置可以被布置为行和列并且可以互连以满足各种应用的要求。 功率处理装置的阵列可以在单个基板上制造。

公开(公告)号：WO2021211139A1

公开(公告)日：2021-10-21

申请号：PCT/US2020/028845

申请日：2020-04-17

Applicant: HRL LABORATORIES, LLC

Inventor： HUANG, Biqin

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L29/423 ,  H01L29/10 ,  H01L29/08

Abstract: A vertical field-effect transistor (FET), comprising a first doped region of a first material, said first doped region having a first doping and being formed on a surface of a substrate, a second doped region of said first material, said second doped region having a second doping and being formed on the first doped region, and a third doped region of said first material, said third doped region having a third doping and being formed on the second doped region, wherein the first doped region has a first width along a first direction parallel to said surface of the substrate, the second doped region has a second width along said first direction, the third doped region has a third width along said first direction, the second width being smaller than the first and third widths.

公开(公告)号：WO2019152090A1

公开(公告)日：2019-08-08

申请号：PCT/US2018/062342

申请日：2018-11-21

Applicant: HRL LABORATORIES, LLC

Inventor： HUANG, Biqin ,  BAI, Xiwei

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/311 ,  H01L21/265 ,  H01L21/304 ,  H01L29/78 ,  H01L29/66

Abstract: A method for fabricating an electrically isolated diamond nanowire includes forming a diamond nanowire on a diamond substrate, depositing a dielectric or a polymer on the diamond nanowire and on the diamond substrate, planarizing the dielectric or the polymer, etching a portion of the planarized dielectric or polymer to expose a first portion of the diamond nanowire, depositing a metal layer to conformably cover the first portion of the diamond nanowire, and implanting ions into a second portion of the diamond nanowire between the first portion of the diamond nanowire and the diamond substrate or at an intersection of the diamond nanowire and the diamond, substrate, wherein the ions are implanted at an oblique angle from a first side of the diamond nanowire.

公开(公告)号：WO2018231494A1

公开(公告)日：2018-12-20

申请号：PCT/US2018/034462

申请日：2018-05-24

Applicant: HRL LABORATORIES, LLC

Inventor： HUANG, Biqin

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/739

Abstract: Presented is a lateral fin static induction transistor including a semi conductive substrate, source and drain regions extending from an optional buffer layer of same or varied thickness supported by the semi conductive substrate, a semi conductive channel electrically coupling the source region to the drain region of the transistor, a portion of the semi conductive channel being a fin and having a face covered by a gated structure, thereby defining a gated channel within the semi conductive channel, the semi conductive channel further including a drift region electrically coupling the gated channel to the drain region of the transistor.