公开(公告)号：WO2016206406A1

公开(公告)日：2016-12-29

申请号：PCT/CN2016/075859

申请日：2016-03-08

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： YANG, Li ,  PAN, Huapu ,  BAI, Yusheng ,  SHEN, Xiao Andy

IPC: G02B6/42 ,  G02B6/122

CPC classification number: G02B6/14 ,  G02B6/1228 ,  G02B6/136 ,  G02B6/305

Abstract: A method includes forming a first optical structure with an inverse taper and a separate optical structure on a semiconductor chip. The illustrative method also includes applying a protective structure over the optical structures and patterning the protective structure to expose the separate optical structure. The method further includes removing a portion of the separate optical structure to form a separate trimmed taper separate from, but adjacent to, the first optical structure. The protective structure is then removed from the first optical structure. Apparatuses are also disclosed.

Abstract translation: 一种方法包括在半导体芯片上形成具有倒锥度的第一光学结构和单独的光学结构。 说明性方法还包括在光学结构上施加保护结构并且图案化保护结构以暴露单独的光学结构。 该方法还包括去除分离的光学结构的一部分以形成与第一光学结构分开但与第一光学结构相邻的单独的修剪锥。 然后从第一光学结构去除保护结构。 还公开了装置。

公开(公告)号：WO2019179466A1

公开(公告)日：2019-09-26

申请号：PCT/CN2019/078897

申请日：2019-03-20

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： ZHENG, Dawei ,  YI, Ge ,  YANG, Li ,  SHEN, Xiao

IPC: G02B6/136

Abstract: A method for fabricating a photonic integrated circuit (PIC) comprises providing a silicon-on-insulator (SOI) wafer comprising an insulator layer disposed between a base semiconductor layer and a SOI layer, wherein the SOI layer comprises a waveguide, providing at least one slot within the SOI layer, wherein the at least one slot is positioned on the same or opposite sides of the waveguide, and wherein the at least one slot is positioned at a predetermined distance away from the waveguide, and removing a portion of the insulator layer to form an etched-out portion of the insulator layer, wherein the etched-out portion is positioned directly beneath the waveguide, and wherein a width of the etched-out portion is at least the width of the waveguide

公开(公告)号：WO2015168419A1

公开(公告)日：2015-11-05

申请号：PCT/US2015/028538

申请日：2015-04-30

Applicant: HUAWEI TECHNOLOGIES CO., LTD. ,  FUTUREWEI TECHNOLOGIES, INC.

Inventor： YANG, Li ,  PAN, Huapu ,  XU, Qianfan ,  ZHENG, Dawei ,  SHEN, Xiao

IPC: G02B6/30 ,  G02B6/122 ,  G02B6/14

CPC classification number: G02B6/14 ,  G02B6/1228 ,  G02B6/132 ,  G02B6/136 ,  G02B6/305

Abstract: An apparatus comprises a substrate comprising a silicon dioxide (SiO2) material disposed on top of the substrate, a silicon waveguide comprising a first adiabatic tapering and enclosed in the silicon dioxide material, and a low-index waveguide disposed on top of the substrate and adjacent to the first adiabatic tapering. A mode converter fabrication method comprises obtaining a mode converter comprising a substrate, a silicon waveguide disposed on the substrate and comprising a sidewall and a first adiabatic tapering, and a hard mask disposed on the silicon waveguide and comprising a silicon dioxide (SiO2) layer, wherein the hard mask does not cover the sidewall, and oxidizing the silicon waveguide and the hard mask, wherein oxidizing the silicon waveguide and the hard mask encloses the silicon waveguide within the silicon dioxide layer.

Abstract translation: 一种装置包括：衬底，其包括设置在衬底顶部的二氧化硅（SiO 2）材料，包括第一绝热锥形并封装在二氧化硅材料中的硅波导，以及设置在衬底顶部和相邻的低折射率波导 到第一个绝热锥形。 一种模式转换器制造方法，包括：获得模式转换器，包括基板，设置在基板上的硅波导，包括侧壁和第一绝热锥形，以及设置在硅波导上并包括二氧化硅（SiO 2）层的硬掩模， 其中所述硬掩模不覆盖所述侧壁，并且氧化所述硅波导和所述硬掩模，其中氧化所述硅波导和所述硬掩模将所述硅波导包围在所述二氧化硅层内。

公开(公告)号：WO2015161207A1

公开(公告)日：2015-10-22

申请号：PCT/US2015/026386

申请日：2015-04-17

Applicant: HUAWEI TECHNOLOGIES CO., LTD. ,  FUTUREWEI TECHNOLOGIES, INC.

Inventor： CHEN, Hongmin ,  XU, Qianfan ,  YANG, Li ,  SHEN, Xiao

IPC: G02F1/025 ,  G02B6/12

CPC classification number: G02F1/025 ,  G02B6/13 ,  G02B2006/12061 ,  G02B2006/12142 ,  G02F2001/0151 ,  H01L29/0649 ,  H01L29/167 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/518 ,  H01L29/66181 ,  H01L29/94

Abstract: A metal-oxide semiconductor (MOS) optical modulator including a doped semiconductor layer having a waveguide structure, a dielectric layer disposed over the waveguide structure of the doped semiconductor layer, a gate region disposed over the dielectric layer, wherein the gate region comprises a transparent electrically conductive material having a refractive index lower than that of silicon, and a metal contact disposed over the gate region. The metal contact, the gate region, and the waveguide structure of the doped semiconductor layer may be vertically aligned with each other.

Abstract translation: 一种金属氧化物半导体（MOS）光学调制器，包括具有波导结构的掺杂半导体层，设置在掺杂半导体层的波导结构之上的电介质层，设置在电介质层上的栅极区，其中栅极区包括透明 具有低于硅的折射率的导电材料和设置在栅极区域上的金属接触。 掺杂半导体层的金属接触，栅极区域和波导结构可以彼此垂直对准。

公开(公告)号：WO2016161882A1

公开(公告)日：2016-10-13

申请号：PCT/CN2016/076630

申请日：2016-03-17

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： WEI, Hongzhen ,  YANG, Li ,  XU, Qianfan ,  SHEN, Xiao Andy

IPC: G02F1/025

CPC classification number: G02F1/025 ,  G02F2001/0151 ,  G02F2001/0152 ,  H01L21/2253 ,  H01L21/30604 ,  H01L21/3215

Abstract: A silicon waveguide (110) comprising a waveguide core (118) that comprises a first positively doped region (111), also refers to as P1 region, vertically adjacent to a second positively doped region (112), also refers to as P2 region, The P2 region (112) is more heavily positively doped than the P1 region (111). A first negatively doped region (114), also refers to as N1 region, is vertically adjacent to a second negatively doped region (113), and also refers to as N2 region. The N2 region (113) is more heavily negatively doped than the N1 region (114). The N2 region (113) and the P2 region (112) are positioned vertically adjacent to form a PN junction. The N1 region (114), the N2 region (113), the P1 region (111), and the P2 region (112) are positioned as a vertical PN junction and configured to completely deplete the P2 region (112) of positive ions and completely deplete the N2 region (113) of negative ions when a voltage drop is applied across the N1 region (114), the N2 region (113), the P1 region (111), and the P2 region (112).

Abstract translation: 包括包括第一正掺杂区域（111）的波导芯（118）的硅波导（110）也指与第二正掺杂区域（112）垂直相邻的P1区域，也称为P2区域， P2区（112）比P1区（111）更重的正掺杂。 第一负掺杂区域（114）也指N1区域与第二负掺杂区域（113）垂直相邻，并且也指N2区域。 N2区域（113）比N1区域（114）更负重地掺杂。 N2区域（113）和P2区域（112）垂直相邻地形成PN结。 N1区域（114），N2区域（113），P1区域（111）和P2区域（112）被定位为垂直PN结并且被配置为完全耗尽正离子的P2区域（112） 当跨越N1区域（114），N2区域（113），P1区域（111）和P2区域（112）施加电压降时，完全耗尽负离子的N2区域（113）。