公开(公告)号：WO2019133172A1

公开(公告)日：2019-07-04

申请号：PCT/US2018/063054

申请日：2018-11-29

Applicant: INTEL CORPORATION

Inventor： WEISSMANN, Eliezer ,  GENDLER, Alexander ,  ROTEM, Efraim ,  COHEN, Moshe ,  MALLICK, Asit K. ,  BRANDT, Jason, W. ,  SUBRAMANIAM, Kameswar ,  FELLMAN, Nathan ,  SHAFI, Hisham

IPC: G06F13/36

Abstract: Processor, method, and system for reducing latency in accessing remote registers is described herein. One embodiment of a processor includes one or more remote registers and remote register access circuitry. The remote register access circuitry is to detect a request from the requestor to access a first register of the one or more remote registers, access to the first register in accordance to the request without the requestor having to wait for completion of the access, and provide a notification accessible to the requestor upon completion of the access to the first register of the one or more remote registers.