公开(公告)号：WO2019133172A1

公开(公告)日：2019-07-04

申请号：PCT/US2018/063054

申请日：2018-11-29

Applicant: INTEL CORPORATION

Inventor： WEISSMANN, Eliezer ,  GENDLER, Alexander ,  ROTEM, Efraim ,  COHEN, Moshe ,  MALLICK, Asit K. ,  BRANDT, Jason, W. ,  SUBRAMANIAM, Kameswar ,  FELLMAN, Nathan ,  SHAFI, Hisham

IPC: G06F13/36

Abstract: Processor, method, and system for reducing latency in accessing remote registers is described herein. One embodiment of a processor includes one or more remote registers and remote register access circuitry. The remote register access circuitry is to detect a request from the requestor to access a first register of the one or more remote registers, access to the first register in accordance to the request without the requestor having to wait for completion of the access, and provide a notification accessible to the requestor upon completion of the access to the first register of the one or more remote registers.

公开(公告)号：WO2013101059A1

公开(公告)日：2013-07-04

申请号：PCT/US2011/067838

申请日：2011-12-29

Applicant: INTEL CORPORATION ,  VAN DE VEN, Adriaan ,  PATEL, Baiju, V. ,  MALLICK, Asit, K. ,  NEIGER, Gilbert ,  COKE, James, S. ,  DIXON, Martin, G. ,  BRANDT, Jason, W.

Inventor： VAN DE VEN, Adriaan ,  PATEL, Baiju, V. ,  MALLICK, Asit, K. ,  NEIGER, Gilbert ,  COKE, James, S. ,  DIXON, Martin, G. ,  BRANDT, Jason, W.

IPC: G06F21/22 ,  G06F9/30

CPC classification number: G06F9/30189 ,  G06F9/30043 ,  G06F12/0292 ,  G06F12/1009 ,  G06F12/1491

Abstract: Apparatuses and methods for supervisor mode execution protection are disclosed. In one embodiment, a processor includes an interface to access a memory, execution hardware, and control logic. A region in the memory is user memory. The execution hardware is to execute an instruction. The control logic is to prevent the execution hardware from executing the instruction when the instruction is stored in user memory and the processor is in supervisor mode.

Abstract translation: 公开了用于监督模式执行保护的装置和方法。 在一个实施例中，处理器包括访问存储器，执行硬件和控制逻辑的接口。 存储器中的区域是用户存储器。 执行硬件是执行指令。 当指令存储在用户存储器中并且处理器处于主管模式时，控制逻辑是防止执行硬件执行指令。

公开(公告)号：WO2013095473A1

公开(公告)日：2013-06-27

申请号：PCT/US2011/066665

申请日：2011-12-21

Applicant: INTEL CORPORATION ,  GROBMAN, Steven, L. ,  BRANDT, Jason, W.

Inventor： GROBMAN, Steven, L. ,  BRANDT, Jason, W.

IPC: H04L9/16 ,  H04L9/08

CPC classification number: H04L9/0861 ,  G06F21/60 ,  H04L9/0631 ,  H04L9/0822 ,  H04L9/0877 ,  H04L2209/127 ,  H04L2209/24

Abstract: Systems and methods for protecting symmetric encryption keys when performing encryption are described. In one embodiment, a computer-implemented method includes retrieving at least one real key from a secure area and executing, with a processor, a key transform instruction to generate at least one transformed key based on receiving the at least one real key. The at least one transformed key is an encrypted version of at least one round key that is encrypted by the processor using the at least one real key. The processor is able to decrypt the at least one transformed key and encrypt the at least one round key.

Abstract translation: 描述了在执行加密时保护对称加密密钥的系统和方法。 在一个实施例中，计算机实现的方法包括从安全区域检索至少一个真实密钥，并且利用处理器执行密钥变换指令，以基于接收所述至少一个真实密钥来生成至少一个变换密钥。 至少一个变换密钥是由处理器使用至少一个真实密钥加密的至少一个循环密钥的加密版本。 处理器能够对至少一个变换的密钥进行解密并加密至少一个循环密钥。

公开(公告)号：WO2013081607A1

公开(公告)日：2013-06-06

申请号：PCT/US2011/062673

申请日：2011-11-30

Applicant: INTEL CORPORATION ,  COMBS, Jonathan, D. ,  BRANDT, Jason, W. ,  VALENTINE, Robert ,  SMITH, Kevin, B. ,  ANSARI, Zia ,  LOKTYUKHIN, Maxim

Inventor： COMBS, Jonathan, D. ,  BRANDT, Jason, W. ,  VALENTINE, Robert ,  SMITH, Kevin, B. ,  ANSARI, Zia ,  LOKTYUKHIN, Maxim

IPC: G06F9/30 ,  G06F9/06

CPC classification number: G06F9/3016 ,  G06F9/30072 ,  G06F9/30094 ,  G06F9/30185

Abstract: In one embodiment, a processor includes an instruction decoder to receive a first instruction having a prefix and an opcode and to generate, by an instruction decoder of the processor, a second instruction executable based on a condition determined based on the prefix, and an execution unit to conditionally execute the second instruction based on the condition determined based on the prefix.

Abstract translation: 在一个实施例中，处理器包括指令解码器，用于接收具有前缀和操作码的第一指令，并且由处理器的指令解码器生成基于基于前缀确定的条件的可执行的第二指令，以及执行 基于基于前缀确定的条件来有条件地执行第二指令的单元。