公开(公告)号：WO2018125490A1

公开(公告)日：2018-07-05

申请号：PCT/US2017/063713

申请日：2017-11-29

Applicant: INTEL CORPORATION

Inventor： CONNOR, Patrick ,  DUBAL, Scott P. ,  TAMIR, Eliezer ,  PAVLAS, Chris ,  GASPARAKIS, Iosif ,  HEARN, James R.

IPC: H04L12/931 ,  H04L12/861 ,  H04L12/935

Abstract: An example computer system for transferring a packet includes a hypervisor to run a first virtual machine and a second virtual machine. The computer system also includes a first memory address space associated with the first virtual machine to store the packet. The computer system further includes a second memory address space associated with the second virtual machine to receive and store the packet. The computer system also includes a virtual switch coupled to the first virtual machine and the second virtual machine to detect that the packet is to be sent from the first virtual machine to the second virtual machine. The computer system further includes a direct memory access device to copy the packet from the first memory address space to the second memory address space via the direct memory access device.

公开(公告)号：WO2017099917A1

公开(公告)日：2017-06-15

申请号：PCT/US2016/060790

申请日：2016-11-07

Applicant: INTEL CORPORATION

Inventor： DUBAL, Scott P. ,  LOUZOUN, Eliel ,  BOOM, Douglas D. ,  LUSTED, Kent C. ,  BARBEE, Ronald F. ,  SHAH, Nishantkumar

IPC: G06F13/42 ,  G06F13/40

CPC classification number: G06F13/4068 ,  G06F13/36 ,  G06F13/4282 ,  H04L67/10

Abstract: Methods for implementing mini-mezzanine Open Compute Project (OCP) plug-and-play Network PHY Cards and associated apparatus. In accordance with one aspect, the MAC (Media Access Channel) and PHY (Physical) layer functions in one or more communication protocol stacks are split between a MAC block in a Platform Controller Hub (PCH) or processor SoC and a PHY card installed in a mezzanine slot of a platform and including one or more ports. During platform initialization operations, configuration parameters are read from the PHY card including a PHY card ID, and a corresponding configuration script is selected and executed to configure the PHY card for use in the platform. The configuration parameters are also used to enumerate PCIe devices associated with physical functions and ports supported by the PHY card.

Abstract translation:

实现迷你夹层开放计算项目（OCP）即插即用网络PHY卡和相关设备的方法。 根据一个方面，一个或多个通信协议栈中的MAC（媒体访问信道）和PHY（物理）层功能在平台控制器中心（PCH）或处理器SoC中的MAC块与安装在 平台的夹层槽并包括一个或多个端口。 在平台初始化操作期间，从PHY卡读取包括PHY卡ID的配置参数，并且选择并执行相应的配置脚本以配置用于平台的PHY卡。 配置参数还用于枚举与PHY卡支持的物理功能和端口相关的PCIe设备。

公开(公告)号：WO2018183799A1

公开(公告)日：2018-10-04

申请号：PCT/US2018/025340

申请日：2018-03-30

Applicant: INTEL CORPORATION

Inventor： VEERAMANI, Karthik ,  PAIDIPATHI, Ujwal ,  CHOWDHURY, Rajneesh ,  IYER, Prakash N. ,  MACHNIKOWSKI, Maciej ,  PAVLAS, Chris ,  DUBAL, Scott P.

IPC: H04L29/08 ,  H04L29/06 ,  G06F9/50

Abstract: Systems, apparatuses, and/or methods to provide data processing offload. An apparatus may determine whether a task is to be processed locally at a client device or remotely off the client device and issue the task to a wireless network and/or a wired network when the task is to be processed remotely off the client device at a server device. An apparatus may identify the task from the wireless network and/or the wired network when the task is to be processed locally at the server device, distribute the task to a server resource at the server device when the task is to be to processed locally at the service device, and provide a result of the task to the wireless network and/or the wired network when the result is to be consumed remotely at the client device.

公开(公告)号：WO2018102086A1

公开(公告)日：2018-06-07

申请号：PCT/US2017/060431

申请日：2017-11-07

Applicant: INTEL CORPORATION

Inventor： CONNOR, Patrick ,  DUBAL, Scott P. ,  SAMUDRALA, Sridhar ,  MALA, Praveen ,  LI, Sibai

IPC: G06F13/40 ,  G06F9/30

CPC classification number: G06F21/76 ,  G09C1/00 ,  H04L9/0631 ,  H04L2209/12 ,  H04L2209/76

Abstract: Examples include techniques for a field programmable gate array (FPGA) to perform one or more functions for an application specific integrated circuit (ASIC). Example techniques include communication between the ASIC and the FPGA via a sideband communication link to enable the ASIC to indicate to the FPGA a need for the FPGA to perform a function to fulfill a request received by the ASIC.

公开(公告)号：WO2021257111A1

公开(公告)日：2021-12-23

申请号：PCT/US2020/064670

申请日：2020-12-11

Applicant: INTEL CORPORATION

Inventor： CONNOR, Patrick ,  HEARN, James R. ,  LIEDTKE, Kevin ,  DUBAL, Scott P.

IPC: H04L12/931 ,  G06F9/455 ,  H04L12/803 ,  H04L12/823 ,  H04L29/08 ,  H04L29/06 ,  G06F2009/4557 ,  G06F2009/45583 ,  G06F2009/45595 ,  G06F9/45558 ,  H04L12/4645 ,  H04L47/125 ,  H04L47/32 ,  H04L49/356 ,  H04L63/0227 ,  H04L63/0272 ,  H04L63/1408 ,  H04L63/166 ,  H04L67/02 ,  H04L67/1097 ,  H04L67/34 ,  H04L69/161 ,  H04L69/22

Abstract: Examples described herein relate to a switch device for a rack of two or more physical servers, wherein the switch device is coupled to the two or more physical servers and the switch device performs packet protocol processing termination for received packets and provides payload data from the received packets without a received packet header to a destination buffer of a destination physical server in the rack. In some examples, the switch device comprises at least one central processing unit, the at least one central processing unit is to execute packet processing operations on the received packets. In some examples, a physical server executes at least one virtualized execution environments (VEE) and the at least one central processing unit executes a VEE for packet processing of packets with data to be accessed by the physical server that executes the VEE.

公开(公告)号：WO2017112143A1

公开(公告)日：2017-06-29

申请号：PCT/US2016/062209

申请日：2016-11-16

Applicant: INTEL CORPORATION

Inventor： PALERMO, Stephen T. ,  WILLIS, Thomas E. ,  SOOD, Kapil ,  GANGA, Ilango S. ,  DUBAL, Scott P. ,  GANESH, Pradeepsunder ,  BRANDENBURG, Jesse C.

IPC: H04L12/931 ,  G06F9/455

CPC classification number: G06F9/45558 ,  G06F2009/45595 ,  H04L49/70

Abstract: Methods and Apparatus for Multi-Stage VM Virtual Network Function and Virtual Service Function Chain Acceleration for NFV and needs-based hardware acceleration. Compute platform hosting virtualized environments including virtual machines (VMs) running service applications performing network function virtualization (NFV) employ Field Programmable Gate Array (FPGA) to provide a hardware-based fast path for performing VM-to-VM and NFV-to-NFV transfers. The FPGAs, along with associated configuration data are also configured to support dynamic assignment and performance of hardware-acceleration to offload processing tasks from processors in virtualized environments, such as cloud data centers and the like.

Abstract translation: 用于NFV和基于需求的硬件加速的用于多阶段VM虚拟网络功能和虚拟服务功能链加速的方法和装置 运行虚拟化环境的计算平台，包括运行执行网络功能虚拟化（NFV）的服务应用程序的虚拟机（VM），采用现场可编程门阵列（FPGA）为执行虚拟机到虚拟机和NFV到NFV提供基于硬件的快速路径 传输。 FPGA以及相关的配置数据也被配置为支持硬件加速的动态分配和性能，以将处理任务从诸如云数据中心之类的虚拟化环境中的处理器卸载。