公开(公告)号：WO2012040052A2

公开(公告)日：2012-03-29

申请号：PCT/US2011/051957

申请日：2011-09-21

Applicant: INTEL CORPORATION ,  KUMAR, Pankaj ,  NGUYEN, Hang ,  HOUGHTON, Christopher L. ,  BIERMANN, David

Inventor： KUMAR, Pankaj ,  NGUYEN, Hang ,  HOUGHTON, Christopher L. ,  BIERMANN, David

IPC: G06F1/26 ,  G06F1/00

CPC classification number: G06F1/3296 ,  G05F1/46 ,  G06F1/26 ,  G06F1/3206 ,  G06F1/3228 ,  G06F1/324 ,  G06F9/3016 ,  Y02D10/126 ,  Y02D10/172

Abstract: In one embodiment, the present invention includes a processor having a plurality of cores and a control logic to control provision of a voltage/frequency to a first core of the plurality of cores independently of provision of a voltage/frequency to at least a second core of the plurality of cores. In some embodiments, the voltages may be provided from one or more internal voltage regulators of the processor. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括具有多个内核和控制逻辑的处理器，以控制向多个内核中的第一内核提供电压/频率，而不依赖于提供电压 /频率提供给多个核心中的至少第二核心。 在一些实施例中，电压可以从处理器的一个或多个内部电压调节器提供。 描述并要求保护其他实施例。

公开(公告)号：WO2004061666A2

公开(公告)日：2004-07-22

申请号：PCT/US2003/036345

申请日：2003-11-13

Applicant: INTEL CORPORATION

Inventor： NGUYEN, Hang ,  TU, Steven ,  HONCHARIK, Alexander ,  JAMIL, Sujat

IPC: G06F11/14

CPC classification number: G06F11/1641 ,  G06F11/1654 ,  G06F2201/845

Abstract: A processor includes first and second execution cores that operate in a redundant (FRC) mode, an FRC check unit to compare results from the first and second execution cores, and an error check unit to detect recoverable errors in the first and second cores. The error detector disables the FRC checker, responsive to detection of a recoverable error. A multi-mode embodiment of the processor implements a multi-core mode in addition to the FRC mode. An arbitration unit regulates access to resources shared by the first and second execution cores in multi-core mode. The FRC checker is located proximate to the arbitration unit in the multi-mode embodiment.

Abstract translation: 处理器包括以冗余（FRC）模式操作的第一和第二执行核心，用于比较来自第一和第二执行核心的结果的FRC检查单元和用于检测第一和第二核心中的可恢复错误的错误检查单元。 响应于检测到可恢复的错误，错误检测器禁用FRC检查器。 处理器的多模式实施例除了FRC模式之外还实现多核模式。 仲裁单元以多核心模式来管理由第一和第二执行核共享的资源的访问。 在多模式实施例中，FRC检验器位于仲裁单元附近。

公开(公告)号：WO2006071942A2

公开(公告)日：2006-07-06

申请号：PCT/US2005/047273

申请日：2005-12-28

Applicant: INTEL CORPORATION ,  EDIRISOORIYA, Samantha ,  TU, Steven ,  TSE, Gregory ,  JAMIL, Sujat ,  MINER, David ,  O'BLENESS, Frank ,  NGUYEN, Hang

Inventor： EDIRISOORIYA, Samantha ,  TU, Steven ,  TSE, Gregory ,  JAMIL, Sujat ,  MINER, David ,  O'BLENESS, Frank ,  NGUYEN, Hang

IPC: G06F13/40 ,  G06F13/36

CPC classification number: G06F13/36 ,  G06F13/4022

Abstract: Some embodiments of the invention include an address interconnect and a data interconnect to transfer data among a number of devices. The data interconnect is configured to transfer data among the devices via multiple transfer paths. A transfer of data on one transfer path is independent from a transfer of data on another transfer path. In some cases, data is concurrently transferred among more than two of the devices on at least one of the address interconnect and the data interconnect. Other embodiments are described and claimed.

Abstract translation: 本发明的一些实施例包括地址互连和数据互连以在多个设备之间传输数据。 数据互连被配置为经由多个传输路径在设备之间传输数据。 一条传输路径上的数据传输与另一条传输路径上的数据传输无关。 在某些情况下，数据在至少一个地址互连和数据互连上的多个设备之间同时传输。 描述并要求保护其他实施例。