公开(公告)号：WO2023048804A1

公开(公告)日：2023-03-30

申请号：PCT/US2022/037742

申请日：2022-07-20

申请人： INTEL CORPORATION

发明人： ECTON, Jeremy, D. ,  PIETAMBARAM, Srinivas, V. ,  MARIN, Brandon, C. ,  CHEN, Haobo ,  ARANA, Leonel

IPC分类号： H01L23/498 ,  H01L23/15 ,  H01L23/00 ,  H01L21/48 ,  H01L23/14

摘要： Embodiments include electronic packages and methods of forming such packages. In an embodiment, an electronic package comprises a first substrate, and a second substrate coupled to the first substrate. In an embodiment, the second substrate comprises a core, and the core comprises an organic material. In an embodiment, a third substrate is coupled to the second substrate, and the third substrate comprises a glass layer.

公开(公告)号：WO2023048813A1

公开(公告)日：2023-03-30

申请号：PCT/US2022/038217

申请日：2022-07-25

申请人： INTEL CORPORATION

发明人： DUONG, Benjamin ,  DARMAWIKARTA, Kristof ,  PIETAMBARAM, Srinivas, V. ,  GRUJICIC, Darko ,  NIE, Bai ,  IBRAHIM, Tarek, A. ,  AGRAWAL, Ankur ,  GAAN, Sandeep ,  MAHAJAN, Ravindranath, V. ,  ALEKSOV, Aleksandar

IPC分类号： H01L25/16 ,  H01L25/065 ,  G02B6/124 ,  G02B6/43 ,  G02B6/42 ,  H01L25/00 ,  G02B6/12

摘要： Embodiments disclosed herein include electronic packages and methods of forming such electronic packages. In an embodiment, an electronic package comprises a first layer, where the first layer comprises glass. In an embodiment, a second layer is over the first layer, where the second layer comprises a mold material. In an embodiment, a first photonics integrated circuit (PIC) is within the second layer. In an embodiment, a second PIC is within the second layer, and a waveguide is in the first layer. In an embodiment, the waveguide optically couples the first PIC to the second PIC.

公开(公告)号：WO2023048798A1

公开(公告)日：2023-03-30

申请号：PCT/US2022/037467

申请日：2022-07-18

申请人： INTEL CORPORATION

发明人： COLLINS, Andrew ,  PIETAMBARAM, Srinivas, V. ,  IBRAHIM, Tarek, A. ,  GANESAN, Sanka ,  VISWANATH, Ram, S.

IPC分类号： H01L23/00 ,  H01L23/498 ,  H01L23/15

摘要： Embodiments described herein may be related to apparatuses, processes, and techniques directed to glass core-based substrates with an asymmetric number of front and back-side copper layers. In embodiments, the front and/or backside copper layers may be referred to as stack ups or as buildup layers on the glass core substrate. Embodiments may allow lower overall substrate layer counts by allowing for more front side layers where the signal routing may typically be highest, without requiring a matching, or symmetric, number of backside copper layers. Other embodiments may be described and/or claimed.

公开(公告)号：WO2023048796A1

公开(公告)日：2023-03-30

申请号：PCT/US2022/037331

申请日：2022-07-15

申请人： INTEL CORPORATION

发明人： COLLINS, Andrew ,  PIETAMBARAM, Srinivas, V. ,  GANESAN, Sanka ,  IBRAHIM, Tarek, A. ,  MORTENSEN, Russell

IPC分类号： H01L25/065 ,  H01L23/15 ,  H01L23/498 ,  H01L23/538 ,  H01L25/00

摘要： Embodiments described herein may be related to apparatuses, processes, and techniques directed to packages that include one or more dies that are coupled with one or more glass layers. These glass layers may be within an interposer or a patch to which the one or more dies are attached. In addition, these glass layers may be used to facilitate pitch translation between the one or more dies proximate to a first side of the glass layer and a substrate proximate to a second side of the glass layer opposite the first side, to which the one or more dies are electrically coupled. Other embodiments may be described and/or claimed.