公开(公告)号：WO2017039865A1

公开(公告)日：2017-03-09

申请号：PCT/US2016/043345

申请日：2016-07-21

Applicant: INTEL CORPORATION

Inventor： RAMADOSS, Murali ,  PENDLURU, Nishanth Reddy ,  FRIZZELL, Jeffrey S. ,  SHAH, Ankur N.

IPC: G06T1/20 ,  G06T5/00 ,  G06T1/60

CPC classification number: G06T1/20 ,  G06T1/60 ,  G06T2200/28

Abstract: A mechanism is described for facilitating efficient scheduling of graphics workloads at computing devices. A method of embodiments, as described herein, includes receiving a work request for processing a work item at a graphics processor, where the work request is placed by an application. The method may further include allowing the application to directly call into a graphics driver associated with the graphics processor to generate a work queue for the work item, where direct calling allows the application to bypass an intermediary call to the graphics driver and directly submit the work item to the graphics processor, where direct calling further includes notifying the graphics processor of the work unit by writing into a memory location monitored by the graphics processor. The method may further include submitting the work item from the work queue to a submit queue of a plurality of submit queues, where one or more tasks associated with the work item are processed at the graphics processor.

Abstract translation: 描述了用于促进计算设备处的图形工作负载的有效调度的机制。 如本文所述的实施例的方法包括在图形处理器处接收用于处理工作项的工作请求，其中由应用程序放置工作请求。 该方法还可以包括允许应用程序直接调用与图形处理器相关联的图形驱动程序，以生成工作项目的工作队列，其中直接调用允许应用程序绕过对图形驱动器的中间调用并直接提交工作 项目到图形处理器，其中直接呼叫还包括通过写入由图形处理器监视的存储器位置来通知工作单元的图形处理器。 该方法还可以包括将工作项目从工作队列提交到多个提交队列的提交队列，其中与工作项目相关联的一个或多个任务在图形处理器处理。

公开(公告)号：WO2020190799A2

公开(公告)日：2020-09-24

申请号：PCT/US2020/022837

申请日：2020-03-14

Applicant: INTEL CORPORATION

Inventor： KOKER, Altug ,  RAY, Joydeep ,  ASHBAUGH, Ben ,  PEARCE, Jonathan ,  APPU, Abhishek ,  RANGANATHAN, Vasanth ,  STRIRAMASSARMA, Lakshminarayanan ,  OULD-AHMED-VALL, Elmoustapha ,  ANANTARAMAN, Aravindh ,  ANDREI, Valentin ,  GALOPPO VON BORRIES, Nicolas ,  GEORGE, Varghese ,  HAREL, Yoav ,  HUNTER, Arthur Jr. ,  INSKO, Brent ,  JANUS, Scott ,  K, Pattabhiraman ,  MACPHERSON, Mike ,  MAIYURAN, Subramaniam ,  PETRE, Marian Alin ,  RAMADOSS, Murali ,  SHAH, Shailesh ,  SINHA, Kamal ,  SURTI, Prasoonkumar ,  VEMULAPALLI, Vikranth

IPC: G06F9/38 ,  G06F12/0862 ,  G06F9/30 ,  G06F12/02 ,  G06F12/06 ,  G06F12/0804 ,  G06F12/0893 ,  G06F12/12 ,  G06F12/128 ,  G06F15/173 ,  G06F9/50

Abstract: Systems and methods for improving cache efficiency and utilization are disclosed. In one embodiment, a graphics processor includes processing resources to perform graphics operations and a cache controller of a cache coupled to the processing resources. The cache controller is configured to control cache priority by determining whether default settings or an instruction will control cache operations for the cache.

公开(公告)号：WO2020190426A1

公开(公告)日：2020-09-24

申请号：PCT/US2020/017747

申请日：2020-02-11

Applicant: INTEL CORPORATION ,  COORAY, Niran ,  SADLER, William B. ,  PEARCE, Jonathan D. ,  PETRE, Marian Alin ,  ASHBAUGH, Ben ,  RAMADOSS, Murali ,  VEMULAPALLI, Vikranth ,  SHAH, Ankur N. ,  SANKARAN, Rajesh

Inventor： COORAY, Niran ,  SADLER, William B. ,  PEARCE, Jonathan D. ,  PETRE, Marian Alin ,  ASHBAUGH, Ben ,  RAMADOSS, Murali ,  VEMULAPALLI, Vikranth ,  SHAH, Ankur N. ,  SANKARAN, Rajesh

IPC: G06F9/48 ,  G06F9/46 ,  G06T1/20

Abstract: Methods and apparatus relating to transactional page fault handling. In an example, an apparatus comprises a processor to divide an execution thread of a graphics workload into a set of transactions which are to be executed atomically, initiate the execution of the thread, and manage the execution of the thread according to one of a first protocol in response to a determination that a page fault occurred in the execution of a transaction, or a second protocol in response to a determination that a page fault did not occur in the execution of a transaction. Other embodiments are also disclosed and claimed.

公开(公告)号：WO2017155623A1

公开(公告)日：2017-09-14

申请号：PCT/US2017/015033

申请日：2017-01-26

Applicant: INTEL CORPORATION

Inventor： KUMAR, Arvind ,  VALAVI, John J. ,  RAMADOSS, Murali

IPC: G06F3/0488 ,  G06F3/0486 ,  G06F3/14

CPC classification number: G06F3/0416 ,  G06F1/1616 ,  G06F1/1647 ,  G06F1/1692 ,  G06F3/0412 ,  G06F3/04883 ,  G06F3/04886 ,  G06F9/451

Abstract: An example system for generating hardware device input includes a gesture detector to detect an input device trigger from one of two coupled touch-enabled displays. The example system also further includes a redirector to intercept touch data from a triggered touch-enabled display. The example system further includes an emulator to generate hardware input data based on the intercepted touch data and send the hardware input data to an operating system. The example system also includes a user interface to display a virtual input device on the triggered touch-enabled display and receive touch data via the virtual input device.

Abstract translation: 用于生成硬件设备输入的示例系统包括手势检测器，以从两个耦合的启用触摸的显示器中的一个检测输入设备触发。 该示例系统还进一步包括重定向器，用于从触发的启用触摸的显示器中截取触摸数据。 示例系统进一步包括仿真器，用于基于截取的触摸数据生成硬件输入数据并将硬件输入数据发送到操作系统。 示例系统还包括用户界面，以在触发的启用触摸的显示器上显示虚拟输入设备，并通过虚拟输入设备接收触摸数据。

公开(公告)号：WO2014014628A1

公开(公告)日：2014-01-23

申请号：PCT/US2013/047638

申请日：2013-06-25

Applicant: INTEL CORPORATION ,  VEMBU, Balaji ,  NAVALE, Aditya ,  RAMADOSS, Murali ,  STANDRING, David, I. ,  BALA, Kritika

Inventor： VEMBU, Balaji ,  NAVALE, Aditya ,  RAMADOSS, Murali ,  STANDRING, David, I. ,  BALA, Kritika

IPC: G06F9/46

CPC classification number: G06F9/4881 ,  Y02D10/24

Abstract: A computing device for performing scheduling operations for graphics hardware is described herein. The computing device includes a central processing unit (CPU) that is configured to execute an application. The computing device also includes a graphics scheduler configured to operate independently of the CPU. The graphics scheduler is configured to receive work queues relating to workloads from the application that are to execute on the CPU and perform scheduling operations for any of a number of graphics engines based on the work queues.

Abstract translation: 本文描述了用于执行图形硬件的调度操作的计算设备。 计算设备包括被配置为执行应用的中央处理单元（CPU）。 计算设备还包括被配置为独立于CPU操作的图形调度器。 图形调度器被配置为接收与在CPU上执行的应用程序的工作负载有关的工作队列，并且基于工作队列对多个图形引擎中的任何一个执行调度操作。

公开(公告)号：WO2020190429A1

公开(公告)日：2020-09-24

申请号：PCT/US2020/017897

申请日：2020-02-12

Applicant: INTEL CORPORATION ,  VEMULAPALLI, Vikranth ,  STRIRAMASSARMA, Lakshminarayanan ,  MACPHERSON, Mike ,  ANANTARAMAN, Aravindh ,  ASHBAUGH, Ben ,  RAMADOSS, Murali ,  SADLER, William B. ,  PEARCE, Jonathan ,  JANUS, Scott ,  INSKO, Brent ,  RANGANATHAN, Vasanth ,  SINHA, Kamal ,  HUNTER, Arthur ,  SURTI, Prasoonkumar ,  GALOPPO VON BORRIES, Nicolas ,  RAY, Joydeep ,  APPU, Abhisek R. ,  OULD-AHMED-VALL, ElMoustapha ,  KOKER, Altug ,  KIM, Sungye ,  MAIYURAN, Subramaniam ,  ANDREI, Valentin

Inventor： VEMULAPALLI, Vikranth ,  STRIRAMASSARMA, Lakshminarayanan ,  MACPHERSON, Mike ,  ANANTARAMAN, Aravindh ,  ASHBAUGH, Ben ,  RAMADOSS, Murali ,  SADLER, William B. ,  PEARCE, Jonathan ,  JANUS, Scott ,  INSKO, Brent ,  RANGANATHAN, Vasanth ,  SINHA, Kamal ,  HUNTER, Arthur ,  SURTI, Prasoonkumar ,  GALOPPO VON BORRIES, Nicolas ,  RAY, Joydeep ,  APPU, Abhisek R. ,  OULD-AHMED-VALL, ElMoustapha ,  KOKER, Altug ,  KIM, Sungye ,  MAIYURAN, Subramaniam ,  ANDREI, Valentin

IPC: G06F12/0862 ,  G06F12/0897 ,  G06F12/0888 ,  G06F9/38

Abstract: Embodiments are generally directed to data prefetching for graphics data processing. An embodiment of an apparatus includes one or more processors including one or more graphics processing units (GPUs); and a plurality of caches to provide storage for the one or more GPUs, the plurality of caches including at least an L1 cache and an L3 cache, wherein the apparatus to provide intelligent prefetching of data by a prefetcher of a first GPU of the one or more GPUs including measuring a hit rate for the L1 cache; upon determining that the hit rate for the L1 cache is equal to or greater than a threshold value, limiting a prefetch of data to storage in the L3 cache, and upon determining that the hit rate for the L1 cache is less than a threshold value, allowing the prefetch of data to the L1 cache.

公开(公告)号：WO2020190422A1

公开(公告)日：2020-09-24

申请号：PCT/US2020/017521

申请日：2020-02-10

Applicant: INTEL CORPORATION ,  RAMADOSS, Murali ,  VEMULAPALLI, Vikranth ,  COORAY, Niran ,  SADLER, William B. ,  PEARCE, Jonathan D. ,  PETRE, Marian Alin ,  ASHBAUGH, Ben ,  OULD-AHMED-VALL, ElMoustapha ,  GALOPPO VON BORRIES, Nicolas ,  KOKER, Altug ,  ANANTARAMAN, Aravindh ,  MAIYURAN, Subramaniam ,  GEORGE, Varghese ,  KIM, Sungye ,  VALENTIN, Andrei

Inventor： RAMADOSS, Murali ,  VEMULAPALLI, Vikranth ,  COORAY, Niran ,  SADLER, William B. ,  PEARCE, Jonathan D. ,  PETRE, Marian Alin ,  ASHBAUGH, Ben ,  OULD-AHMED-VALL, ElMoustapha ,  GALOPPO VON BORRIES, Nicolas ,  KOKER, Altug ,  ANANTARAMAN, Aravindh ,  MAIYURAN, Subramaniam ,  GEORGE, Varghese ,  KIM, Sungye ,  VALENTIN, Andrei

IPC: G06F9/50 ,  G06F12/08

Abstract: Methods and apparatus relating to predictive page fault handling. In an example, an apparatus comprises a processor to receive a virtual address that triggered a page fault for a compute process, check a virtual memory space for a virtual memory allocation for the compute process that triggered the page fault and manage the page fault according to one of a first protocol in response to a determination that the virtual address that triggered the page fault is a last page in the virtual memory allocation for the compute process, or a second protocol in response to a determination that the virtual address that triggered the page fault is not a last page in the virtual memory allocation for the compute process. Other embodiments are also disclosed and claimed.

公开(公告)号：WO2019067072A1

公开(公告)日：2019-04-04

申请号：PCT/US2018/043685

申请日：2018-07-25

Applicant: INTEL CORPORATION

Inventor： SAMSON, Eric C. ,  RAMADOSS, Murali ,  BEUCHAT, Marc

IPC: G06F1/32 ,  G06T1/20

Abstract: Methods and apparatus relating to advanced graphics Power State management are described. In one embodiment, measurement logic detects information about idle transitions and active transitions of a power-well of a processor. In turn, determination logic determines performance loss and/or energy gain based at least in part on the detected information and power-on latency of the power-well of the processor. Other embodiments are also disclosed and claimed.

公开(公告)号：WO2018057240A1

公开(公告)日：2018-03-29

申请号：PCT/US2017/048786

申请日：2017-08-27

Applicant: INTEL CORPORATION

Inventor： KRISHNAN, Vidhya ,  COORAY, Niranjan L. ,  RAMADOSS, Murali

IPC: G06F12/1009 ,  G06T1/20

Abstract: A virtual-to-virtual page table maps a main surface containing the actual data and a metadata or auxiliary surface that gives information about compression of the main surface. In order to access the metadata that corresponds to main surface, an additional virtual-to-virtual table may be used ahead of the regular page table mapping to avoid the need to pass the metadata base address and x, y coordinates across a pipeline which may result in multiple memory writes.

Abstract translation: 虚拟到虚拟页面表映射包含实际数据的主表面和提供关于主表面的压缩的信息的元数据或辅助表面。 为了访问与主表面相对应的元数据，可以在常规页表映射之前使用额外的虚拟到虚拟表，以避免需要将元数据基地址和x，y坐标通过管道传递 导致多次写入内存。

公开(公告)号：WO2017052949A1

公开(公告)日：2017-03-30

申请号：PCT/US2016/048524

申请日：2016-08-25

Applicant: INTEL CORPORATION

Inventor： RAMADOSS, Murali ,  VEMBU, Balaji ,  NALLURI, Hema C. ,  APODACA, Michael ,  BOLES, Jeffery S.

IPC: G06T1/20 ,  G06T1/60 ,  G06T15/08 ,  G06T17/10

CPC classification number: G06T15/80 ,  G06F9/48 ,  G06T1/20

Abstract: By scheduling/managing workload submission to a POSH pipe one can exploit parallelism with minimum impact to the software scheduler in some embodiments. Software separates command sequences for each pipe to enable the POSH pipe to run ahead of a Render pipe. Infrastructre is provided to synchronize the two pipes through software inserted commands. A Render plus POSH pipeline may be a single monolithic engine without changes to a software scheduler, removing the complexity and the latencies involved in scheduling.

Abstract translation: 通过调度/管理到POSH管道的工作负载，可以在一些实施例中利用对软件调度器的最小影响的并行性。 软件分离每个管道的命令序列，以使POSH管道能够在渲染管道之前运行。 提供了基础设施，通过软件插入的命令来同步两个管道。 渲染加POSH管道可以是单个单片引擎，而不改变软件调度器，消除了调度中涉及的复杂性和延迟。