公开(公告)号：WO2018063262A1

公开(公告)日：2018-04-05

申请号：PCT/US2016/054556

申请日：2016-09-29

Applicant: INTEL CORPORATION

Inventor： HSU, Hao-Han ,  HAN, Dong-Ho ,  WACHTMAN, Steven C. ,  KUHLMANN, Ryan K.

IPC: H01L23/552 ,  H01L23/64 ,  H01L23/00 ,  H01L23/66

Abstract: A semiconductor package and a packaged electronic device are described. The semiconductor package has a foundation layer and a planar filtering circuit. The circuit is formed in the foundation layer to provide EMI/RFI mitigation. The circuit has one or more conductive traces that are patterned to form an equivalent circuit of inductors and capacitors. The one or more conductive traces include planar metal shapes, such as meanders, loops, inter-digital fingers, and patterned shapes, to reduce the z-height of the package. The packaged electronic device has a semiconductor die, a foundation layer, a motherboard, a package, and the circuit. The circuit removes undesirable interferences generated from the semiconductor die. The circuit has a z-height that is less than a z-height of solder balls used to attach the foundation layer to the motherboard. A method of forming a planar filtering circuit in a foundation layer is also described.

Abstract translation: 描述了半导体封装和封装的电子器件。 半导体封装具有基础层和平面滤波电路。 该电路形成在基层中以提供EMI / RFI缓解。 该电路具有一个或多个图案化的导电迹线以形成电感器和电容器的等效电路。 一个或多个导电迹线包括平面金属形状，诸如曲折线，环形，数字间指状物和图案化形状，以减小封装的z高度。 封装的电子器件具有半导体管芯，基础层，主板，封装和电路。 该电路去除了从半导体管芯产生的不希望的干扰。 该电路的z高度小于用于将基础层连接到主板的焊球的z高度。 还描述了在基础层中形成平面滤波电路的方法。