公开(公告)号：WO0013227A3

公开(公告)日：2000-06-02

申请号：PCT/EP9905600

申请日：1999-08-03

Applicant: KONINKL PHILIPS ELECTRONICS NV

Inventor： EMONS CATHARINA H H ,  TERPSTRA DOEDE ,  TIMMERING CORNELIS E ,  DE BOER WIEBE B

IPC: H01L21/22 ,  H01L21/223 ,  H01L21/225 ,  H01L21/331 ,  H01L21/8222 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/732 ,  H01L29/737

CPC classification number: H01L29/66287 ,  H01L21/223 ,  H01L21/2252 ,  H01L29/66242

Abstract: The invention relates to a method of manufacturing a discrete or integrated bipolar transistor comprising a base (1A), an emitter (2) and a collector (3). The base (1A) and a connecting region (1B) of the base (1A) are formed by providing a semiconductor body (10) with a doped semiconducting layer (1) which locally borders on a monocrystalline part (3) of the semiconductor body which forms the collector (3). Outside said base, the layer (1) borders on a non-monocrystalline part (4) of the semiconductor body (10) and forms a non-monocrystalline connecting region (1B) of the base (1A). By means of a mask (5), the doping concentration of the layer (1) outside the mask (5) is selectively increased, resulting in a highly conducting connection region (1B) and a very fast transistor. In the known method, an ion implantation is used for this purpose. In a method in accordance with the invention, this is achieved by bringing the semiconductor body (10) into contact with a gaseous substance (40) comprising a doping element, and heating the semiconductor body (10) in such a manner that the doping elements penetrate into the semiconducting layer (1). The supply of the gaseous substance (40), for example diborane, preferably takes place at a temperature between 800 and 950 DEG C for one to several minutes. Subsequently, a slightly longer diffusion step can be carried out, for example, at 850 DEG C.

Abstract translation: 本发明涉及一种制造离散或集成双极晶体管的方法，其包括基极（1A），发射极（2）和集电极（3）。 通过为半导体本体（10）提供半导体本体（1）的单晶部分（3）上的掺杂半导体层（1）来形成基极（1A）的基极（1A）和连接区域（1B） 其形成收集器（3）。 在所述基底之外，层（1）与半导体本体（10）的非单晶部分（4）相接合，并形成基底（1A）的非单晶连接区域（1B）。 通过掩模（5），选择性地增加掩模（5）外的层（1）的掺杂浓度，导致高导电连接区域（1B）和非常快的晶体管。 在已知的方法中，为此目的使用离子注入。 在根据本发明的方法中，这是通过使半导体本体（10）与包括掺杂元素的气态物质（40）接触并且以这样的方式加热半导体本体（10）来实现的，即掺杂元件 渗透到半导体层（1）中。 气态物质（40）例如乙硼烷的供应优选在800-950℃的温度下进行1至数分钟。 随后，稍长的扩散步骤可以在例如850℃下进行。

公开(公告)号：WO9953553A3

公开(公告)日：2000-01-20

申请号：PCT/IB9900567

申请日：1999-04-01

Applicant: KONINKL PHILIPS ELECTRONICS NV ,  PHILIPS SVENSKA AB

Inventor： BROWN ADAM R ,  HURKX GODEFRIDUS A M ,  PETER MICHAEL S ,  HUIZING HENDRIK G A ,  DE BOER WIEBE B

IPC: H01L29/861 ,  H01L29/32 ,  H01L29/885

CPC classification number: H01L29/885 ,  H01L29/32 ,  Y10S438/979

Abstract: The invention relates to a semiconductor device having a rectifying junction (5) which is situated between two (semiconductor) regions (1, 2) of an opposite conductivity type. The second region (2), which includes silicon, is thicker and has a smaller doping concentration than the first region (1) which includes a sub-region comprising a mixed crystal of silicon and germanium. The two regions (1, 2) are each provided with a connection conductor (3, 4). Such a device can very suitably be used as a switching element, in particular as a switching element for a high voltage and/or high power. In the known device, the silicon-germanium mixed crystal is relaxed, leading to the formation of misfit dislocations. These serve to reduce the service life of the minority charge carriers, thus enabling the device to be switched very rapidly. In a device in accordance with the invention, the entire first region (1) comprises a mixed crystal of silicon and germanium, and the germanium content and the thickness of the first region (1) are selected so that the voltage built up in the semiconductor device remains below the level at which misfit dislocations develop. Surprisingly, it has been found that such a device can also be switched very rapidly, even more rapidly than the known device. The absence of misfit dislocations has an additional advantage, namely that the device is very reliable. Misfit dislocations do not develop if the product of said relative deviation in the lattice constant and the thickness of the first region is smaller than or equal to 40 nm %. A safe upper limit for said product is 30 nm %.

Abstract translation: 本发明涉及一种半导体器件，其具有位于相反导电型的两个（半导体）区域（1,2）之间的整流结（5）。 包括硅的第二区域（2）比第一区域（1）更厚并且具有更小的掺杂浓度，该第一区域包括包含硅和锗的混合晶体的子区域。 两个区域（1,2）各自设置有连接导体（3,4）。 这种装置可以非常适合地用作开关元件，特别是用作高电压和/或高功率的开关元件。 在已知的器件中，硅 - 锗混晶被放宽，导致失配位错的形成。 这些用于减少少数电荷载体的使用寿命，从而使装置能够非常快速地切换。 在根据本发明的装置中，整个第一区域（1）包括硅和锗的混合晶体，并且选择锗含量和第一区域（1）的厚度，使得在半导体中积聚的电压 器件仍然低于发生错配位错的水平。 令人惊讶的是，已经发现，这种装置也可以非常快速地切换，甚至比已知装置更快地切换。 没有错配位错具有额外的优点，即该装置非常可靠。 如果晶格常数相对偏差和第一区域的厚度的乘积小于或等于40nm％，则不会发生失配位错。 所述产品的安全上限为30nm％。