公开(公告)号：WO9940630A2

公开(公告)日：1999-08-12

申请号：PCT/IB9900171

申请日：1999-01-28

Applicant: KONINKL PHILIPS ELECTRONICS NV ,  PHILIPS SVENSKA AB

Inventor： HURKX GODEFRIDUS A M ,  SCHLIGTENHORST HOLGER ,  SIEVERS BERND

IPC: H01L29/73 ,  H01L21/331 ,  H01L21/8222 ,  H01L27/06 ,  H01L29/10 ,  H01L29/732

CPC classification number: H01L29/1004 ,  H01L29/7322 ,  Y10S257/927 ,  Y10S257/928

Abstract: The invention relates to a semiconductor device comprising a preferably discrete bipolar transistor with a collector region (1), a base region (2), and an emitter region (3) which are provided with connection conductors (6, 7, 8). A known means of preventing a saturation of the transistor is that the latter is provided with a Schottky clamping diode. The latter is formed in that case in that the connection conductor (7) of the base region (2) is also put into contact with the collector region (1). In a device according to the invention, the second connection conductor (7) is exclusively connected to the base region (2), and a partial region (2B) of that portion (2A) of the base region (2) which lies outside the emitter region (3), as seen in projection, lying below the second connection conductor (7) is given a smaller flux of dopant atoms. The bipolar transistor in a device according to the invention is provided with a pn clamping diode which is formed between the partial region (2B) and the collector region (1). Such a device has excellent properties, such as a short switching time (ts) and a saturation collector-emitter voltage (VCEsat) which is not too high, while having a low, non-variable and well reproducible leakage current, unlike the known device. The reduced flux of dopant atoms of the partial region (2B) is preferably realized in that the partial region (2B) is given a smaller doping concentration and/or thickness than the remainder (2A) of the portion of the base region (2) which lies outside the emitter region (3). In a favourable modification, a region (4) provided simultaneously with the emitter region (3) is present between the partial region (2B) and the second connection conductor (7).

Abstract translation: 本发明涉及一种半导体器件，其包括具有集电极区域（1），基极区域（2）和设置有连接导体（6,7,8）的发射极区域（3））的优选分立的双极晶体管。 防止晶体管饱和的已知方法是后者具有肖特基钳位二极管。 在这种情况下，后者形成为基部区域（2）的连接导体（7）也与集电区（1）接触。 在根据本发明的装置中，第二连接导体（7）专门连接到基部区域（2），并且基部区域（2）的部分（2A）的局部区域（2B）位于 发射极区域（3），如在投影中所看到的，位于第二连接导体（7）下方的给定较小的掺杂剂原子通量。 根据本发明的器件中的双极晶体管设置有形成在部分区域（2B）和集电极区域（1）之间的pn钳位二极管。 这种器件具有优异的性能，例如开关时间短（ts）和饱和集电极 - 发射极电压（VCEsat），其不是太高，而具有低的，不可变的和良好重现的漏电流，与已知的器件不同 。 优选地，实现部分区域（2B）的掺杂剂原子的减小的通量，其中部分区域（2B）被给予比基极区域（2）的部分的其余部分（2A）更小的掺杂浓度和/或厚度， 其位于发射极区域（3）的外部。 在有利的变型中，与发射极区域（3）同时设置的区域（4）存在于部分区域（2B）和第二连接导体（7）之间。

公开(公告)号：WO9953553A3

公开(公告)日：2000-01-20

申请号：PCT/IB9900567

申请日：1999-04-01

Applicant: KONINKL PHILIPS ELECTRONICS NV ,  PHILIPS SVENSKA AB

Inventor： BROWN ADAM R ,  HURKX GODEFRIDUS A M ,  PETER MICHAEL S ,  HUIZING HENDRIK G A ,  DE BOER WIEBE B

IPC: H01L29/861 ,  H01L29/32 ,  H01L29/885

CPC classification number: H01L29/885 ,  H01L29/32 ,  Y10S438/979

Abstract: The invention relates to a semiconductor device having a rectifying junction (5) which is situated between two (semiconductor) regions (1, 2) of an opposite conductivity type. The second region (2), which includes silicon, is thicker and has a smaller doping concentration than the first region (1) which includes a sub-region comprising a mixed crystal of silicon and germanium. The two regions (1, 2) are each provided with a connection conductor (3, 4). Such a device can very suitably be used as a switching element, in particular as a switching element for a high voltage and/or high power. In the known device, the silicon-germanium mixed crystal is relaxed, leading to the formation of misfit dislocations. These serve to reduce the service life of the minority charge carriers, thus enabling the device to be switched very rapidly. In a device in accordance with the invention, the entire first region (1) comprises a mixed crystal of silicon and germanium, and the germanium content and the thickness of the first region (1) are selected so that the voltage built up in the semiconductor device remains below the level at which misfit dislocations develop. Surprisingly, it has been found that such a device can also be switched very rapidly, even more rapidly than the known device. The absence of misfit dislocations has an additional advantage, namely that the device is very reliable. Misfit dislocations do not develop if the product of said relative deviation in the lattice constant and the thickness of the first region is smaller than or equal to 40 nm %. A safe upper limit for said product is 30 nm %.

Abstract translation: 本发明涉及一种半导体器件，其具有位于相反导电型的两个（半导体）区域（1,2）之间的整流结（5）。 包括硅的第二区域（2）比第一区域（1）更厚并且具有更小的掺杂浓度，该第一区域包括包含硅和锗的混合晶体的子区域。 两个区域（1,2）各自设置有连接导体（3,4）。 这种装置可以非常适合地用作开关元件，特别是用作高电压和/或高功率的开关元件。 在已知的器件中，硅 - 锗混晶被放宽，导致失配位错的形成。 这些用于减少少数电荷载体的使用寿命，从而使装置能够非常快速地切换。 在根据本发明的装置中，整个第一区域（1）包括硅和锗的混合晶体，并且选择锗含量和第一区域（1）的厚度，使得在半导体中积聚的电压 器件仍然低于发生错配位错的水平。 令人惊讶的是，已经发现，这种装置也可以非常快速地切换，甚至比已知装置更快地切换。 没有错配位错具有额外的优点，即该装置非常可靠。 如果晶格常数相对偏差和第一区域的厚度的乘积小于或等于40nm％，则不会发生失配位错。 所述产品的安全上限为30nm％。

公开(公告)号：WO9946821A3

公开(公告)日：1999-11-25

申请号：PCT/IB9900202

申请日：1999-02-04

Applicant: KONINKL PHILIPS ELECTRONICS NV ,  PHILIPS SVENSKA AB

Inventor： SCHLIGTENHORST HOLGER ,  HURKX GODEFRIDUS A M ,  WARWICK ANDREW M

IPC: H01L29/73 ,  H01L21/329 ,  H01L21/331 ,  H01L29/732 ,  H01L29/868 ,  H01L21/04 ,  H01L29/772

CPC classification number: H01L29/66136 ,  H01L29/66295 ,  H01L29/7325 ,  H01L29/868

Abstract: In a semiconductor switch device such as an NPN transistor (T) or a power switching diode (D), a multiple-zone first region (1) of one conductivity type forms a switchable p-n junction (12) with a second region (2) of opposite conductivity type. In accordance with the invention, this first region (1) includes three distinct zones, namely a low-doped zone (23), a high-doped zone (25), and an intermediate additional zone (24). The low-doped zone (23) is provided by a semiconductor body portion (11) having a substantially uniform p-type doping concentration (P-) and forms the p-n junction (12) with the second region (2). The distinct additional zone (24) is present between the low-doped zone (23) and the high-doped zone (25). This triple-zone formation for the first region (1) permits an improvement in switching behaviour, e.g. in terms of fall-time and energy dissipation during turn-off of the device (T, D). A very low doping (P-) can be used for low-doped zone (23) so that, in the off-state of the device (T, D), this zone (23) and also the additional zone (24) can be fully depleted. The additional zone (24) having its additional doping concentration provides a path for extracting residual charge carriers from the low-doped zone (23) when the device (T, D) is being switched off.

Abstract translation: 在诸如NPN晶体管（T）或功率开关二极管（D）的半导体开关器件中，一个导电类型的多区域第一区域（1）形成具有第二区域（2）的可切换pn结（12） 的相反导电类型。 根据本发明，该第一区域（1）包括三个不同的区域，即低掺杂区域（23），高掺杂区域（25）和中间附加区域（24）。 低掺杂区域（23）由具有基本均匀的p型掺杂浓度（P-）的半导体本体部分（11）提供，并与第二区域（2）形成p-n结（12）。 不同的附加区（24）存在于低掺杂区（23）和高掺杂区（25）之间。 用于第一区域（1）的这种三区形成允许改变开关行为，例如， 在设备（T，D）关闭期间的下降时间和能量耗散方面。 对于低掺杂区域（23），可以使用非常低的掺杂（P-），使得在器件（T，D）的截止状态下，该区域（23）以及附加区域（24）可以 充分耗尽 具有其附加掺杂浓度的附加区域（24）提供了当器件（T，D）被切断时从低掺杂区域（23）提取残余电荷载流子的路径。

公开(公告)号：WO0161762A2

公开(公告)日：2001-08-23

申请号：PCT/EP0100773

申请日：2001-01-24

Applicant: KONINKL PHILIPS ELECTRONICS NV

Inventor： HURKX GODEFRIDUS A M ,  HIJZEN EDWIN A

IPC: H01L21/28 ,  H01L29/861

CPC classification number: H01L29/8618

Abstract: The invention relates to a so-called punch-through diode comprising a stack of, for example, an n , p , p , n region (1, 2, 3, 4). In the known diode, these regions (1, 2, 3, 4) are arranged on a substrate (11) in said order. The diode is provided with connection conductors (5, 6). Such a diode does not have a steep I-V characteristic and hence is less suitable as a TVSD (= Transient Voltage Suppression Device). Particularly at voltages below 5 volts, a punch-through diode could form an attractive alternative for use as a TVSD. A punch-through diode according to the invention has an inverted structure, which means that the regions (1, 2, 3, 4) are positioned in reverse order on the substrate (11) and thus, the first region (1) adjoins the surface, and the fourth region (4) adjoins the substrate (11). Such a diode has a very steep I-V characteristic, is very suitable as a TVSD and functions very well at an operating voltage below 5 volts. Preferably, the diode is provided with a field plate (6) and, also preferably, the first region (1) comprises a mixed crystal of silicon and germanium.

Abstract translation: 本发明涉及一种所谓的穿通二极管，其包括例如n +，p +，p +，n ++区（1,2,3）， 4）。 在已知的二极管中，这些区域（1,2,3,4）按照该顺序排列在基板（11）上。 二极管设有连接导体（5,6）。 这样的二极管不具有陡峭的I-V特性，因此不太适合作为TVSD（=瞬态电压抑制装置）。 特别是在低于5伏的电压下，穿通二极管可以形成用作TVSD的有吸引力的替代方案。 根据本发明的穿通二极管具有倒置结构，这意味着区域（1,2,3,4）以相反的顺序位于衬底（11）上，因此第一区域（1）邻接 表面，第四区域（4）与衬底（11）相邻。 这种二极管具有非常陡峭的I-V特性，非常适合作为TVSD，并且在低于5伏特的工作电压下功能非常好。 优选地，二极管设置有场板（6），并且还优选地，第一区域（1）包括硅和锗的混合晶体。

公开(公告)号：WO02065552A3

公开(公告)日：2002-12-19

申请号：PCT/IB0200431

申请日：2002-02-13

Applicant: KONINKL PHILIPS ELECTRONICS NV

Inventor： VAN DALEN ROB ,  ROCHEFORT CHRISTELLE ,  HURKX GODEFRIDUS A M

IPC: H01L29/47 ,  H01L21/336 ,  H01L21/8234 ,  H01L27/04 ,  H01L27/06 ,  H01L27/088 ,  H01L29/06 ,  H01L29/40 ,  H01L29/78 ,  H01L29/861 ,  H01L29/872 ,  H01L29/41

CPC classification number: H01L29/405 ,  H01L29/407 ,  H01L29/408 ,  H01L29/7802 ,  H01L29/7813 ,  H01L29/861 ,  H01L29/872

Abstract: A semiconductor device, such as a power MOSFET, Schottky rectifier or p-n rectifier, has a voltage-sustaining zone (20) between a first (21, 23, 31a) and second (22) device regions adjacent to respective first and second opposite surfaces (11, 12) of a semiconductor body 10. Trenched field-shaping regions (40) including a resistive path (42) extend through the voltage-sustaining zone (20) to the underlying second region (22), so as to enhance the breakdown voltage of the device. The voltage-sustaining zone (20) and the trenched field-shaping regions (40) are present in both the active device area (A) and in the peripheral area (P) of the device. A further resistive path (53) extends across the first surface (11), outwardly over the peripheral area (P). This further resistive path (53) provides a potential divider that is connected to the respective resistive paths (42) of successive underlying trenched field-shaping regions (40) in the peripheral area (P). Thereby a gradual variation is achieved in the potential (V2) applied by the successive trenched field-shaping regions (40) in the peripheral area (P) of the voltage-sustaining zone (20). This advantageous peripheral termination reduces device susceptibility to deviations in the field profile in this peripheral area (P).

Abstract translation: 诸如功率MOSFET，肖特基整流器或pn整流器的半导体器件在与相应的第一和第二相对表面相邻的第一（21,23a）和第二（22）器件区域之间具有电压维持区域（20） （11,12）。包括电阻路径（42）的有沟槽的场整形区域（40）延伸通过所述电压维持区域（20）延伸到下面的第二区域（22），以便增强 器件的击穿电压。 电压维持区域（20）和沟槽场整形区域（40）存在于器件的有源器件区域（A）和外围区域（P）中。 另一电阻路径（53）跨越第一表面（11）延伸，在外围区域（P）上方向外延伸。 该另外的电阻路径（53）提供了一个分压器，其连接到周边区域（P）中连续的下游沟槽场整形区域（40）的相应的电阻路径（42）。 由此，在由维持电压区（20）的周边区域（P）中的连续沟槽场整形区域（40）施加的电位（V2）中实现了逐渐变化。 这种有利的外围终端降低了该外围区域（P）中场分布偏差的装置敏感性。

公开(公告)号：WO0159844A3

公开(公告)日：2002-01-10

申请号：PCT/EP0100830

申请日：2001-01-26

Applicant: KONINKL PHILIPS ELECTRONICS NV

Inventor： HURKX GODEFRIDUS A M ,  VAN DALEN ROB

IPC: H01L29/06 ,  H01L29/40 ,  H01L29/47 ,  H01L29/861 ,  H01L29/872

CPC classification number: H01L29/408 ,  H01L29/861 ,  H01L29/872

Abstract: A semiconductor device has first and second opposed major surfaces (10a and 10b). A semiconductor first region (11) is provided between second (12 or 120) and third (14) regions such that the second region (12 or 120) forms a rectifying junction (13 or 130) with the first region (11) and separates the first region (11) from the first major surface (10a) while the third region (14) separates the first region (11) from the second major surface (10b). A plurality of semi-insulating or resistive paths (21) are dispersed within the first region (1') such that each path extends through the first region from the second to the third region. In use of the device when a reverse biasing voltage is applied across the rectifying junction (13 or 130) an electrical potential distribution is generated along the resistive paths (21) which causes a depletion region in the first region (11) to extend through the first region (11) to the third region (14) to increase the reverse breakdown voltage of the device. The device may be, for example a pn-n diode in which case the second region is a semiconductive region of the opposite conductivity type to the first region or a Schottky diode in which case the second region (120) forms a Schottky contact with the first region.

Abstract translation: 半导体器件具有第一和第二相对的主表面（10a和10b）。 半导体第一区域（11）设置在第二（12或120）和第三（14）区域之间，使得第二区域（12或120）与第一区域（11）形成整流结（13或130） 所述第一区域（11）从所述第一主表面（10a）移动，而所述第三区域（14）将所述第一区域（11）与所述第二主表面（10b）分离。 多个半绝缘或电阻路径（21）分散在第一区域（1'）内，使得每条路径从第二区域延伸穿过第一区域。 当在整流结（13或130）两端施加反向偏置电压时，在使用该器件时，电阻分布沿着电阻通道（21）产生，这导致第一区域（11）中的耗尽区延伸通过 第一区域（11）到第三区域（14），以增加器件的反向击穿电压。 器件可以是例如pn-n二极管，在这种情况下，第二区域是与第一区域相反的导电类型的半导体区域或肖特基二极管，在这种情况下，第二区域（120）形成肖特基接触 第一区。

公开(公告)号：WO02067332A3

公开(公告)日：2003-02-20

申请号：PCT/IB0200478

申请日：2002-02-15

Applicant: KONINKL PHILIPS ELECTRONICS NV

Inventor： VAN DALEN ROB ,  ROCHEFORT CHRISTELLE ,  HURKX GODEFRIDUS A M

IPC: H01L27/04 ,  H01L21/822 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/78 ,  H01L29/861 ,  H01L29/41

CPC classification number: H01L29/405 ,  H01L29/408 ,  H01L29/41766 ,  H01L29/7802 ,  H01L29/7813 ,  H01L29/861

Abstract: A semiconductor device, such as a MOSFET or PN diode rectifier, has a p-n junction (24) between a first device region (23) and an underlying voltage-sustaining zone (20). Trenched field-shaping regions (40) extend through the voltage-sustaining zone (20) to improve the voltage-blocking and on-resistance characteristics of the device. The trenched field-shaping region (40) comprises a resistive path (42) accommodated in a trench (41) that has an insulating layer (44) at its side-walls. The insulating layer (44) dielectrically couples potential from the resistive path (42) to the voltage-sustaining zone (20) that is depleted in a voltage-blocking mode of operation of the device. The insulating layer (44) extends at the side-walls of the trench (41) to an upper level (81) that is higher than a lower level (82) at which the resistive path (42) starts in the trench (41). This lower level (82) is more closely aligned to the p-n junction (24) and is protected by the insulating layer (44) extending to the higher level (81). This construction enables the electric field distribution in the voltage-sustaining zone (20) to be improved by aligning very closely the start of the potential drop along the resistive path (42) with the p-n junction depth (d).

Abstract translation: 诸如MOSFET或PN二极管整流器的半导体器件在第一器件区域（23）和下伏电压维持区（20）之间具有p-n结（24）。 倾斜的场成形区域（40）延伸通过电压维持区域（20），以改善装置的压阻和导通电阻特性。 沟槽场整形区域（40）包括容纳在其侧壁上具有绝缘层（44）的沟槽（41）中的电阻路径（42）。 绝缘层（44）将电阻从电阻路径（42）介电地耦合到耗尽该器件的电压阻断模式的电压维持区（20）。 绝缘层（44）在沟槽（41）的侧壁处延伸到高于电阻路径（42）在沟槽（41）中开始的较低电平（82）的上电平（81） 。 该较低电平（82）与p-n结（24）更紧密地对准，并被延伸到较高电平（81）的绝缘层（44）保护。 这种结构使得能够通过非常接近地沿着电阻路径（42）与p-n结深度（d）非常接近的电位降的起始来提高电压维持区（20）中的电场分布。

公开(公告)号：WO0159847A3

公开(公告)日：2002-03-28

申请号：PCT/EP0100913

申请日：2001-01-29

Applicant: KONINKL PHILIPS ELECTRONICS NV

Inventor： HURKX GODEFRIDUS A M ,  VAN DALEN ROB

IPC: H01L29/06 ,  H01L29/40 ,  H01L29/78 ,  H01L29/41

CPC classification number: H01L29/405 ,  H01L29/0634 ,  H01L29/402 ,  H01L29/408 ,  H01L29/7802

Abstract: A semiconductor body (10) has first and second opposed major surfaces (10a and 10b), with a first region (11) of one conductivity type and a plurality of body regions (32) of the opposite conductivity type each forming a pn junction with the first region (11). A plurality of source regions (33) meet the first major surface (10a) and are each associated with a corresponding body region (32) such that a conduction channel accommodating portion (33a) is defined between each source region (33) and the corresponding body region (32). An insulated gate structure (30,31) adjoins each conduction channel area (33a) for controlling formation of a conduction channel in the conduction channel areas to control majority charge carrier flow from the source regions (33) through the first region (11) to a further region (14) adjoining the second major surface (10b). A plurality of field shaping regions (20) are dispersed within the first region (11) and extend from the source regions (32) towards the further region (14) such that, in use, a voltage is applied between the source and further regions (33 and 14) and the device is non-conducting, the field shaping regions (20) provide a path for charge carriers from the source regions at least partially through the first region and cause a depletion region in the first region (11) to extend through the first region (11) towards the further region (14) to increase the reverse breakdown voltage of the device.

Abstract translation: 半导体本体（10）具有第一和第二相对的主表面（10a和10b），具有一个导电类型的第一区域（11）和相反导电类型的多个体区域（32），每个都形成具有 第一区（11）。 多个源极区域（33）与第一主表面（10a）相遇并且分别与相应的主体区域（32）相关联，使得导电沟道容纳部分（33a）被限定在每个源极区域（33）和相应的 身体区域（32）。 绝缘栅极结构（30,31）邻接每个导电沟道区域（33a），用于控制导电沟道区域中的导电沟道的形成，以控制从源极区域（33）穿过第一区域（11）的多数电荷载流子流到 与第二主表面（10b）相邻的另一区域（14）。 多个场成形区域（20）分散在第一区域（11）内并且从源极区域（32）朝向另外的区域（14）延伸，使得在使用中在源极和其它区域之间施加电压 （33和14），并且器件是非导通的，场成形区域（20）至少部分地通过第一区域提供来自源极区的电荷载流子的路径，并且使第一区域（11）中的耗尽区域 延伸穿过第一区域（11）朝向另外的区域（14），以增加装置的反向击穿电压。

公开(公告)号：WO0033386A3

公开(公告)日：2000-11-16

申请号：PCT/EP9908951

申请日：1999-11-16

Applicant: KONINKL PHILIPS ELECTRONICS NV

Inventor： HURKX GODEFRIDUS A M ,  HUETING RAYMOND J E

IPC: H01L21/225 ,  H01L21/336 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L29/0634 ,  H01L21/2255 ,  H01L29/42368 ,  H01L29/7813

Abstract: In a trench-gate semiconductor device, for example a cellular power MOSFET, the gate (11) is present in a trench (20) that extends through the channel-accommodating region (15) of the device. An underlying body portion (16) that carries a high voltage in an off state of the device is present adjacent to a side wall of a lower part (20b) of the trench (20). Instead of being a single high-resistivity region, this body portion (16) comprises first regions (61) of a first conductivity type interposed with second regions (62) of the opposite second conductivity type. In the conducting state of the device, the first regions (61) provide parallel current paths through the thick body portion (16), from the conduction channel (12) in the channel-accommodating region (15). In an off-state of the device, the body portion (16) carries a depletion layer (50). The first region (61) of this body portion (16) is present between the second region (62) and the side wall (22) of the lower part (20b) of the trench (20) and has a doping concentration (Nd) of the first conductivity type that is higher than the doping concentration (Na) of the second conductivity type of the second region (62). A balanced space charge is nonetheless obtained by depletion of the first and second regions (61, 62), because the width (W1) of the first region (61) is made smaller than the width (W2) of the lower-doped second region (62). This device structure can have a low on-resistance and high breakdown voltage, while also permitting its commercial manufacture using dopant out-diffusion from the lower trench part (20b) into the lower-doped second region (62) to form the first region (61).

Abstract translation: 在沟槽栅极半导体器件（例如蜂窝功率MOSFET）中，栅极（11）存在于延伸穿过器件的沟道容纳区域（15）的沟槽（20）中。 在器件的断开状态下承载高电压的下部主体部分（16）与沟槽（20）的下部（20b）的侧壁相邻。 代替单个高电阻率区域，该主体部分（16）包括插入与相对的第二导电类型的第二区域（62）的第一导电类型的第一区域（61）。 在器件的导通状态下，第一区域（61）从通道容纳区域（15）中的导电通道（12）提供穿过厚体部分（16）的平行电流路径。 在装置的关闭状态下，主体部分（16）承载耗尽层（50）。 本体部分（16）的第一区域（61）存在于沟槽（20）的下部（20b）的第二区域（62）和侧壁（22）之间，并具有掺杂浓度（Nd） 的第一导电类型，其高于第二区域（62）的第二导电类型的掺杂浓度（Na）。 然而，由于使第一区域（61）的宽度（W1）小于下掺杂第二区域（61）的宽度（W2），因此第一和第二区域（61,62）的耗尽可以获得均衡的空间电荷 （62）。 该器件结构可以具有低的导通电阻和高的击穿电压，同时还允许使用从下沟槽部分（20b）向下掺杂的第二区域（62）的掺杂剂扩散的商业制造以形成第一区域 61）。

公开(公告)号：WO0060644A2

公开(公告)日：2000-10-12

申请号：PCT/EP0002089

申请日：2000-03-09

Applicant: KONINKL PHILIPS ELECTRONICS NV

Inventor： BROWN ADAM R ,  HUETING RAYMOND J E ,  HURKX GODEFRIDUS A M

IPC: H01L21/331 ,  H01L21/336 ,  H01L29/165 ,  H01L29/739 ,  H01L29/78 ,  H01L

CPC classification number: H01L29/7813 ,  H01L29/165 ,  H01L29/66348 ,  H01L29/7397 ,  Y10S438/97

Abstract: A semiconductor body (1) is provided having a first semiconductor region (3) of one conductivity type separated from a first major surface (5a) by a second semiconductor region (5) of the opposite conductivity type. A trench (7) is etched through the second semiconductor region (5) to an etch stop layer (4) provided in the region of the pn junction between the first (3) and second (5) regions, by using an etching process which enables the etching process to be stopped at the etch stop layer. A gate (8, 9) is provided within the trench (7). A source (12) separated from the first region (3) by the second region (5) is formed adjacent the trench so that a conduction channel area (50) of the second region (5) adjacent the trench provides a conduction path between the source and first regions which is controllable by the gate.

Abstract translation: 半导体本体（1）具有通过相反导电类型的第二半导体区域（5）与第一主表面（5a）分离的一种导电类型的第一半导体区域（3）。 通过使用蚀刻工艺将沟槽（7）通过第二半导体区域（5）蚀刻到设置在第一（3）和第二（5）区域之间的pn结区域中的蚀刻停止层（4），其中 使蚀刻工艺在蚀刻停止层处停止。 在沟槽（7）内设有一个门（8,9）。 与沟槽相邻地形成与第一区域（3）分离的源极（12），使得邻近沟槽的第二区域（5）的导电通道区域（50）提供在第二区域 源极和第一区域，其可由栅极控制。