公开(公告)号：WO2020076732A1

公开(公告)日：2020-04-16

申请号：PCT/US2019/055055

申请日：2019-10-07

Applicant: MICRON TECHNOLOGY, INC.

Inventor： KARDA, Kamal M. ,  GANDHI, Ramanathan ,  LI, Hong ,  LIU, Haitao ,  TANG, Sanh D. ,  SILLS, Scott E. ,  RAMASWAMY, Durai Vishak Nirmal

IPC: H01L29/732 ,  H01L29/423 ,  H01L29/66 ,  H01L21/768

Abstract: A device comprises a vertical transistor including a semiconductive pillar comprising a source region, a drain region, and a channel region extending vertically between the source region and the drain region. The channel region comprises an oxide semiconductor material. The vertical transistor further comprises at least one gate electrode laterally neighboring the semiconductive pillar, a gate dielectric material laterally between the semiconductive pillar and the at least one gate electrode, and void spaces vertically adjacent the gate dielectric material and laterally intervening between the at least one gate electrode and each of the source region and the drain region of the semiconductive pillar. Related devices, electronic systems, and methods are also disclosed.

公开(公告)号：WO2019125711A1

公开(公告)日：2019-06-27

申请号：PCT/US2018/062751

申请日：2018-11-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： TANG, Sanh, D. ,  LI, Hong ,  POELSTRA, Erica, L.

IPC: H01L21/768 ,  H01L21/762 ,  H01L27/06

Abstract: Some embodiments include an assembly having pillars of semiconductor material arranged in rows extending along a first direction. The rows include spacing regions between the pillars. The rows are spaced from one another by gap regions. Two conductive structures are within each of the gap regions and are spaced apart from one another by a separating region. The separating region has a floor section with an undulating surface that extends across semiconductor segments and insulative segments. The semiconductor segments have upper surfaces which are above upper surfaces of the insulative segments; Transistors include channel regions within the pillars of semiconductor material, and include gates within the conductive structures. Some embodiments include methods for forming integrated circuitry.