公开(公告)号：WO2010111072A2

公开(公告)日：2010-09-30

申请号：PCT/US2010/027507

申请日：2010-03-16

Applicant: MICRON TECHNOLOGY, INC. ,  TANG, Sanh D. ,  NGUYEN, Mike N.

Inventor： TANG, Sanh D. ,  NGUYEN, Mike N.

IPC: H01L27/108 ,  H01L21/8242

CPC classification number: H01L27/10802 ,  H01L27/1203 ,  H01L29/66833 ,  H01L29/7841

Abstract: Methods, devices, and systems are disclosed for a memory cell having a floating body. A memory cell may include a transistor over an insulation layer and including a source, and a drain. The memory cell may also include a floating body including a first region positioned between the source and the drain, a second region positioned remote from each of the source and drain, and a passage and extending through the insulation layer and coupling the first region to the second region. Additionally, the memory cell includes a bias gate at least partially surrounding the second region and configured for operably coupling to a bias voltage. Furthermore, the memory cell may include a plurality of dielectric layers, wherein each outer vertical surface of the second region has a dielectric layer of the plurality adjacent thereto.

Abstract translation: 公开了具有浮体的存储单元的方法，装置和系统。 存储单元可以包括绝缘层上的晶体管，并且包括源极和漏极。 存储单元还可以包括浮动体，其包括位于源极和漏极之间的第一区域，远离源极和漏极中的每一个定位的第二区域，以及通过并延伸穿过绝缘层的第二区域，并将第一区域耦合到 第二区。 另外，存储器单元包括偏置栅极，至少部分地围绕第二区域并且被配置为可操作地耦合到偏置电压。 此外，存储单元可以包括多个电介质层，其中第二区域的每个外垂直表面具有与其相邻的多个电介质层。

公开(公告)号：WO2021225805A1

公开(公告)日：2021-11-11

申请号：PCT/US2021/028943

申请日：2021-04-23

Applicant: MICRON TECHNOLOGY, INC.

Inventor： YANG, Litao ,  PULUGURTHA, Srinivas ,  GAO, Yunfei ,  TANG, Sanh D. ,  LIU, Haitao

IPC: H01L27/108 ,  H01L27/11504 ,  H01L27/11507 ,  H01L21/8234

Abstract: Some embodiments include an integrated assembly having an array of vertically-extending active regions. Each of the active regions is contained within a four-sided area. Conductive gate material is configured as first conductive structures. Each of the first conductive structures extends along a row of the array. The first conductive structures include segments along three of the four sides of each of the four-sided areas. Second conductive structures are under the active regions and extend along columns of the array. Third conductive structures extend along the rows of the array and are adjacent the fourth sides of the four-sided areas. Storage-elements are coupled with the active regions. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：WO2020076732A1

公开(公告)日：2020-04-16

申请号：PCT/US2019/055055

申请日：2019-10-07

Applicant: MICRON TECHNOLOGY, INC.

Inventor： KARDA, Kamal M. ,  GANDHI, Ramanathan ,  LI, Hong ,  LIU, Haitao ,  TANG, Sanh D. ,  SILLS, Scott E. ,  RAMASWAMY, Durai Vishak Nirmal

IPC: H01L29/732 ,  H01L29/423 ,  H01L29/66 ,  H01L21/768

Abstract: A device comprises a vertical transistor including a semiconductive pillar comprising a source region, a drain region, and a channel region extending vertically between the source region and the drain region. The channel region comprises an oxide semiconductor material. The vertical transistor further comprises at least one gate electrode laterally neighboring the semiconductive pillar, a gate dielectric material laterally between the semiconductive pillar and the at least one gate electrode, and void spaces vertically adjacent the gate dielectric material and laterally intervening between the at least one gate electrode and each of the source region and the drain region of the semiconductive pillar. Related devices, electronic systems, and methods are also disclosed.

公开(公告)号：WO2012116207A2

公开(公告)日：2012-08-30

申请号：PCT/US2012/026358

申请日：2012-02-23

Applicant: MICRON TECHNOLOGY, INC. ,  TANG, Sanh D. ,  ZAHURAK, John K.

Inventor： TANG, Sanh D. ,  ZAHURAK, John K.

IPC: H01L21/8247 ,  H01L27/115

CPC classification number: H01L27/11556 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/04 ,  H01L29/167 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/7889 ,  H01L29/792 ,  H01L29/7926

Abstract: Methods of forming multi-tiered semiconductor devices are described, along with apparatus and systems that include them. In one such method, an opening is formed in a tier of semiconductor material and a tier of dielectric. A portion of the tier of semiconductor material exposed by the opening is processed so that the portion is doped differently than the remaining semiconductor material in the tier. At least substantially all of the remaining semiconductor material of the tier is removed, leaving the differently doped portion of the tier of semiconductor material as a charge storage structure. A tunneling dielectric is formed on a first surface of the charge storage structure and an an intergate dielectric is formed on a second surface of the charge storage structure. Additional embodiments are also described.

Abstract translation: 描述形成多层半导体器件的方法以及包括它们的装置和系统。 在一种这样的方法中，在半导体材料层和电介质层中形成开口。 通过开口暴露的半导体材料层的一部分被处理，使得该部分与该层中剩余的半导体材料不同地掺杂。 至少基本上所有剩余的层的半导体材料被去除，留下半导体材料层的不同掺杂部分作为电荷存储结构。 在电荷存储结构的第一表面上形成隧道电介质，并且在电荷存储结构的第二表面上形成隔间电介质。 还描述了另外的实施例。

公开(公告)号：WO2020149917A1

公开(公告)日：2020-07-23

申请号：PCT/US2019/058827

申请日：2019-10-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： LIU, Haitao ,  KARDA, Kamal M. ,  SANDHU, Gurtej S. ,  TANG, Sanh D. ,  GODA, Akira ,  XU, Lifang

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/792 ,  H01L29/66

Abstract: A memory can have a stacked memory array that can have a plurality of levels of memory cells. Each respective level of memory cells can be commonly coupled to a respective access line. A plurality of drivers can be above the stacked memory array. Each respective driver can have a monocrystalline semiconductor with a conductive region coupled to a respective access line.

公开(公告)号：WO2012125610A2

公开(公告)日：2012-09-20

申请号：PCT/US2012/028878

申请日：2012-03-13

Applicant: MICRON TECHNOLOGY, INC. ,  TANG, Sanh D. ,  SILLS, Scott E. ,  WEST, Whitney L. ,  GOODWIN, Rob B. ,  SINHA, Nishant

Inventor： TANG, Sanh D. ,  SILLS, Scott E. ,  WEST, Whitney L. ,  GOODWIN, Rob B. ,  SINHA, Nishant

IPC: H01L21/28 ,  H01L21/8239

CPC classification number: H01L45/1266 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76858 ,  H01L21/76877 ,  H01L21/76882 ,  H01L21/76883 ,  H01L23/53247 ,  H01L23/53252 ,  H01L45/04 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/142 ,  H01L45/143 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1608 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of forming conductive elements, such as interconnects and electrodes, for semiconductor structures and memory cells. The methods include forming a first conductive material and a second conductive material comprising silver in a portion of at least one opening and performing a polishing process to fill the at least one opening with at least one of the first and second conductive materials. An annealing process may be performed to form a mixture or an alloy of the silver and the material. The methods enable formation of silver containing conductive elements having reduced dimensions (e.g., less than about 20 nm). The resulting conductive elements have a desirable resistivity. The methods may be used, for example, to form interconnects for electrically connecting active devices and to form electrodes for memory cells. A semiconductor structure and a memory cell including such a conductive structure are also disclosed.

Abstract translation: 为半导体结构和存储单元形成诸如互连和电极之类的导电元件的方法。 该方法包括在至少一个开口的一部分中形成包含银的第一导电材料和第二导电材料，并执行抛光工艺以用第一导电材料和第二导电材料中的至少一个填充该至少一个开口。 可以执行退火工艺以形成银和材料的混合物或合金。 该方法能够形成尺寸减小（例如，小于约20nm）的含银导电元件。 所得的导电元件具有理想的电阻率。 例如，该方法可用于形成用于电连接有源器件并形成用于存储器单元的电极的互连。 还公开了包括这种导电结构的半导体结构和存储单元。

公开(公告)号：WO2020181049A1

公开(公告)日：2020-09-10

申请号：PCT/US2020/021115

申请日：2020-03-05

Applicant: MICRON TECHNOLOGY, INC.

Inventor： KARDA, Kamal M. ,  LIU, Haitao ,  RAMASWAMY, Durai Vishak Nirmal ,  GAO, Yunfei ,  TANG, Sanh D. ,  PANDEY, Deepak Chandra

IPC: H01L27/108

Abstract: Some embodiments include an integrated assembly having a carrier-sink-structure, and having digit lines over the carrier-sink-structure. Transistor body regions are over the digit lines. Extensions extend from the carrier-sink-structure to the transistor body regions. The extensions are configured to drain excess carriers from the transistor body regions. Lower source/drain regions are between the transistor body regions and the digit lines, and are coupled with the digit lines. Upper source/drain regions are over the transistor body regions, and are coupled with storage elements. Gates are adjacent the transistor body regions. The transistor body regions, lower source/drain regions and upper source/drain regions are together comprised a plurality of transistors. The transistors and the storage elements are together comprised by a plurality of memory cells of a memory array. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：WO2020040954A1

公开(公告)日：2020-02-27

申请号：PCT/US2019/044286

申请日：2019-07-31

Applicant: MICRON TECHNOLOGY, INC.

Inventor： GUO, Song ,  TANG, Sanh D. ,  TEMCHENKO, Vlad ,  SRIVASTAVA, Shivani

IPC: H01L27/108

Abstract: A method of forming a device comprises forming a patterned masking material comprising parallel structures and parallel trenches extending at a first angle from about 30º to about 75º relative to a lateral direction. A mask is provided over the patterned masking material and comprises additional parallel structures and parallel apertures extending at a second, different angle from about 0º to about 90º relative to the lateral direction. The patterned masking material is further patterned using the mask to form a patterned masking structure comprising elongate structures separated by the parallel trenches and additional parallel trenches. Exposed portions of a hard mask material underlying the patterned masking structure are subjected to ARDE to form a patterned hard mask material. Exposed portions of a semiconductive material underlying the patterned hard mask material are removed to form semiconductive pillar structures. Devices and electronic systems are also described.

公开(公告)号：WO2011053731A2

公开(公告)日：2011-05-05

申请号：PCT/US2010/054564

申请日：2010-10-28

Applicant: MICRON TECHNOLOGY, INC. ,  TANG, Sanh D. ,  ZAHURAK, John K.

Inventor： TANG, Sanh D. ,  ZAHURAK, John K.

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L27/2409 ,  H01L21/22 ,  H01L27/0207 ,  H01L27/2436 ,  H01L27/249 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/144 ,  H01L45/146

Abstract: Non volatile memory devices comprising a memory string including a plurality of vertically superimposed diodes. Each of the diodes may be arranged at different locations along a length of the electrode and may be spaced apart from adjacent diodes by a dielectric material. The electrode may electrically couple the diodes of the memory strings to one another and to another memory device, such as, a MOSFET device. Methods of forming the non volatile memory devices as well as intermediate structures are also disclosed.

Abstract translation: 包括包含多个垂直叠加二极管的存储器串的非易失性存储器件。 每个二极管可以布置在沿着电极的长度的不同位置处，并且可以通过电介质材料与相邻的二极管间隔开。 电极可以将存储串的二极管彼此电耦合并且耦合到另一个存储器器件，例如MOSFET器件。 还公开了形成非易失性存储器件的方法以及中间结构。

公开(公告)号：WO2008030588A1

公开(公告)日：2008-03-13

申请号：PCT/US2007/019592

申请日：2007-09-07

Applicant: MICRON TECHNOLOGY, INC. ,  TANG, Sanh D. ,  HALLER, Gordon ,  DOYLE, Daniel H.

Inventor： TANG, Sanh D. ,  HALLER, Gordon ,  DOYLE, Daniel H.

IPC: H01L21/8242 ,  H01L27/108 ,  H01L29/78 ,  G11C11/401 ,  H01L21/763

CPC classification number: H01L29/7841 ,  G11C11/401 ,  G11C2211/4016 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10844

Abstract: One-transistor (IT) (104) capacitor-less DRAM cells (100) each include a MOS transistor (104) having a bias gate layer (106) that separates a floating body- region (108) from a bulk base substrate (102). The MOS transistor functions as a storage device, eliminating the need of the storage capacitor. Logic "1" is written to and stored in the storage device by causing majority carriers (holes in an NMOS transistor) to accumulate and be held in the floating body region next to the bias gate layer, and is erased by removing the majority carriers from where they are held.

Abstract translation: 单晶体管（IT）（104）无电容器DRAM单元（100）每个都包括具有偏置栅极层（106）的MOS晶体管（104），所述偏置栅极层将浮体区域（108）与大块基板 ）。 MOS晶体管用作存储器件，不需要存储电容器。 通过使多数载波（NMOS晶体管中的空穴）累积并保持在偏置栅极层旁边的浮动体区域中，将逻辑“1”写入并存储在存储装置中，并且通过从多个载流子 他们在哪里举行。