公开(公告)号：WO1982004364A1

公开(公告)日：1982-12-09

申请号：PCT/US1981000698

申请日：1981-05-26

申请人： MOSTEK CORP ,  PROEBSTING ROBERT JAMES

发明人： MOSTEK CORP

IPC分类号： H03K19/094

CPC分类号： H03K19/017 ,  H03K19/09445

摘要： A split load circuit (44) for driving a high speed load (72) and a low speed load (74) to the same logic state in response to one or more input signals. One input signal is provided to the gate terminals of pull-down transistors (48, 50, 52). The inverse of the input signal is provided to the gate terminals of pull-up transistors (64, 66). The high speed load (72) is connected between the pull-up transistor (64) and the pull-down transistor (50) and the low speed load (74) is connected between the pull-up transistor (66) and the pull-down transistor (52). When the input signal at the input node (46) is driven from one voltage state to another, the loads (72, 74) will be driven at different rates depending upon the capacitance and impedance of the load and the sizes of the pull-up transistors (64, 66) and the pull-down transistors (50, 52). The loads (72, 74) are driven independently such that much smaller pull-up and pull-down transistors can be utilized in place of a single pull-up and single pull-down transistor which would need to be fabricated much larger in order to meet the speed requirement of the high speed load (72) and to charge the high capacitance of the low speed load (74). Further, the power consumption is substantially reduced due to the reduced area of the transistors.

摘要翻译： 一种用于响应于一个或多个输入信号将高速负载（72）和低速负载（74）驱动到相同逻辑状态的分流负载电路（44）。 一个输入信号被提供给下拉晶体管（48,50,52）的栅极端子。 输入信号的反相被提供给上拉晶体管（64,66）的栅极端。 高速负载（72）连接在上拉晶体管（64）和下拉晶体管（50）之间，低速负载（74）连接在上拉晶体管（66）和上拉晶体管 下降晶体管（52）。 当输入节点（46）处的输入信号从一个电压状态驱动到另一个时，负载（72,74）将以不同的速率被驱动，这取决于负载的电容和阻抗以及上拉的大小 晶体管（64,66）和下拉晶体管（50,52）。 负载（72,74）被独立地驱动，使得可以使用更小的上拉和下拉晶体管代替单个上拉和单个下拉晶体管，这将需要被制造得更大，以便 满足高速负载（72）的速度要求，并对低速负载（74）的高电容充电。 此外，由于晶体管的面积减小，功耗大幅降低。

公开(公告)号：WO1982002793A1

公开(公告)日：1982-08-19

申请号：PCT/US1981000137

申请日：1981-02-02

申请人： MOSTEK CORP ,  OTOOLE JAMES E ,  PROEBSTING ROBERT J

发明人： MOSTEK CORP

IPC分类号： G11C11/40

CPC分类号： G11C29/835 ,  G11C29/44

摘要： Test circuit (10) for a semiconductor memory. The semiconductor memory includes a redundant decoder (70) for receiving memory address signals (66, 68) which is connected to a redundant circuit element via a signal line (72). The redundant decoder (70) can be programmed in accordance with the address of a defective circuit element, such that when the decoder (70) is addressed by the memory address signals (66, 68) the decoder (70) selects a predetermined redundant circuit element. The test circuit (10) generates an output signal (14) indicating that the circuit element selected by the decoder (70) is a redundant circuit element. The output signal (14) is applied to an indicator circuit (16) which is enabled in a test mode by an abnormal condition detector (26). The output (18) of indicator circuit (16) is applied to an external pin (20).

摘要翻译： 用于半导体存储器的测试电路（10）。 半导体存储器包括用于经由信号线（72）连接到冗余电路元件的存储器地址信号（66,68）的冗余解码器（70）。 可以根据故障电路元件的地址对冗余解码器（70）进行编程，使得当解码器（70）由存储器地址信号（66,68）寻址时，解码器（70）选择预定的冗余电路 元件。 测试电路（10）产生指示由解码器（70）选择的电路元件是冗余电路元件的输出信号（14）。 输出信号（14）被施加到由异常状态检测器（26）在测试模式中使能的指示器电路（16）。 指示电路（16）的输出（18）被施加到外部引脚（20）。

公开(公告)号：WO1982002792A1

公开(公告)日：1982-08-19

申请号：PCT/US1981000136

申请日：1981-02-02

申请人： MOSTEK CORP ,  OTOOLE JAMES E ,  PROEBSTING ROBERT J

发明人： MOSTEK CORP

IPC分类号： G11C11/40

CPC分类号： G11C29/50 ,  G06F2201/81

摘要： A margin test circuit (10) is provided for a semiconductor memory circuit having a plurality of memory cells (16). Each of the memory cells (16) in one row of cells (16) are interconnected to a word line (14). The margin test circuit (10) further includes a row decoder/driver (12) which receives a variable voltage (V u *) for changing the signal level stored within a memory cell (16) to thereby determine the marginal voltage level at which the memory cell (16) will maintain storage of a signal level. The variable voltage (V u *) is the semiconductor memory circuit main supply source (V u) in normal operation but can be forced to a different voltage during the margin test.

摘要翻译： 为具有多个存储单元（16）的半导体存储器电路提供了裕量测试电路（10）。 一行单元（16）中的每个存储单元（16）互连到字线（14）。 边缘检验电路（10）还包括行解码器/驱动器（12），其接收用于改变存储在存储单元（16）内的信号电平的可变电压（V uC> u *），从而确定边际电压电平 存储单元（16）将保持信号电平的存储。 可变电压（V ucc> u *）是正常操作中的半导体存储器电路主电源（V ucc> u），但是在裕量测试期间可以被强制为不同的电压。

公开(公告)号：WO1982000071A1

公开(公告)日：1982-01-07

申请号：PCT/US1980000805

申请日：1980-06-25

申请人： MOSTEK CORP ,  YOUNG I

发明人： MOSTEK CORP

IPC分类号： H03F03/45

CPC分类号： H03F3/45076 ,  H03F3/3001 ,  H03F3/345

摘要： A differential amplifier (24, 26, 10 and 12) having a feedback network (30, 34, 32, 36 and 38) for increasing common output without loss of gain. Also disclosed is a constant current source (60), and a level shifting network (48, 50, 52 and 54) for shifting the D.C. level of the output signal to a D.C. voltage substantially near that of second current source (44). An output stage (84, 86, 90, 92 and 94) provides low output impedance, low D.C. bias power consumption and high current drive capability.

摘要翻译： 具有用于增加公共输出而不损失增益的反馈网络（30,34,32,36和38）的差分放大器（24,26,10和12）。 还公开了一种恒定电流源（60）和用于将输出信号的直流电平移动到基本上接近第二电流源（44）的直流电压的电平移动网络（48,50,52和54）。 输出级（84,86,90,92和94）提供低输出阻抗，低直流偏置功率消耗和高电流驱动能力。

公开(公告)号：WO1981003568A1

公开(公告)日：1981-12-10

申请号：PCT/US1980000673

申请日：1980-06-02

申请人： MOSTEK CORP ,  PROEBSTING R ,  WILSON D

发明人： MOSTEK CORP

IPC分类号： G11C07/00

CPC分类号： G11C11/4094

摘要： A dynamic random access memory (10) receives a memory address of a row decoder (14) which charges a selected row line (18). When the row line (18) is charged an access transistor (24) in a memory cell (22) is rendered conductive to connect a storage capacitor (26) to a bit line (30). The bit lines (30, 38) are previously set at an equilibration voltage. The voltage on the bit line (30) is driven slightly above the equilibration voltage if a high voltage state had been stored in the capacitor (26) or the voltage on the bit line is driven slightly below the equilibration voltage if a low voltage state had been stored on the capacitor (26). A sense amplifier (44) is connected to the bit lines (30, 38) and upon receipt of a latch signal (L) drives the one of the bit lines (30, 38) having the lower voltage to a low voltage state. A pullup circuit (60) drives the voltage on the remaining bit line of the pair to a high voltage state, restoring the memory storage capacitor (26) to its initial state. After the row line (18) is now discharged trapping the original data state in the storage capacitor (26), precharge transistors (50, 52) then connect together the bit lines (30, 38) through a latch node (46) to share charge between the bit lines (30, 38) and drive the bit lines (30, 38) to the equilibration voltage.

摘要翻译： 动态随机存取存储器（10）接收对选定的行线（18）充电的行解码器（14）的存储器地址。 当行线（18）被充电时，将存储单元（22）中的存取晶体管（24）导通以将存储电容器（26）连接到位线（30）。 位线（30,38）预先设定为平衡电压。 如果电容器（26）中存储高电压状态或位线上的电压略低于平衡电压，则位线（30）上的电压略高于平衡电压，如果低电压状态有 被存储在电容器26上。 读出放大器（44）连接到位线（30,38），并且在接收到具有较低电压的位线（30,38）之一的锁存信号（L）被驱动到低电压状态时。 上拉电路（60）将该对的剩余位线上的电压驱动到高电压状态，将存储器存储电容器（26）恢复到初始状态。 在行线（18）现在放电后，将原始数据状态捕获到存储电容器（26）中之后，预充电晶体管（50,52）然后通过锁存节点（46）将位线（30,38）连接在一起，以共享 位线（30,38）之间的电荷并将位线（30,38）驱动到平衡电压。

公开(公告)号：WO1981003567A1

公开(公告)日：1981-12-10

申请号：PCT/US1980000672

申请日：1980-06-02

申请人： MOSTEK CORP ,  PROEBSTING R

发明人： MOSTEK CORP

IPC分类号： G11C07/00

CPC分类号： G06F11/106 ,  G11C11/406 ,  G11C11/4063 ,  G11C29/48

摘要： A semiconductor dynamic memory circuit (10) includes a memory cell array (38) which includes a plurality of memory cells which are accessed through row and column lines by operation of row and column clock chain signals. A strap (68) is provided to operate the circuit (10) as either a memory which is refreshed according to internally generated addresses or a memory which is refreshed in response to externally supplied memory addresses and is easily incorporated into a memory system which utilizes error detection and correction during the refresh operation. In the absence of the strap (68) a refresh signal (20) refreshes cells of the array (38) in response to the address generated by an internal address counter (82). The circuit (10) accesses a given memory location when an externally supplied address is provided together with a RAS signal (12) and a CAS signal (16). When the strap (68) is incorporated into the circuit (10) the refresh signal (20) applied thereto causes the memory cell array (38) to be refreshed at the externally supplied address. The data within the memory cell array (38) is accessed in response to an externally supplied memory address, the RAS signal (12) and the CAS signal (16). The CAS signal (16) is inhibited in the absence of the RAS signal (12). The circuit (10) is used within a memory array (102) for reading out stored data together with error correcting bits while at the same time refreshing all of the memory circuits in the memory (102). An error detecting and correcting circuit (160) is provided to evaluate the data read out from the memory circuits and to provide a corrected data pattern when erroneous bits are detected.

摘要翻译： 半导体动态存储器电路（10）包括存储单元阵列（38），其包括通过行和列时钟链信号的操作通过行和列线访问的多个存储单元。 提供带（68）以将电路（10）操作为根据内部生成的地址刷新的存储器或响应于外部提供的存储器地址而刷新的存储器，并且容易地并入到利用错误的存储器系统中 在刷新操作期间的检测和校正。 在没有带（68）的情况下，刷新信号（20）响应于由内部地址计数器（82）产生的地址刷新阵列（38）的单元。 当外部提供的地址与RAS信号（12）和CAS信号（16）一起提供时，电路（10）访问给定的存储器位置。 当带（68）被并入到电路（10）中时，施加到其上的刷新信号（20）使得存储单元阵列（38）在外部提供的地址处被刷新。 响应于外部提供的存储器地址RAS信号（12）和CAS信号（16）来访问存储单元阵列（38）内的数据。 在没有RAS信号（12）的情况下，CAS信号（16）被禁止。 电路（10）用在存储器阵列（102）内，用于读出存储的数据以及纠错位，同时刷新存储器（102）中的所有存储器电路。 提供错误检测和校正电路（160）以评估从存储器电路读出的数据，并且当检测到错误位时提供校正的数据模式。

公开(公告)号：WO1981003560A1

公开(公告)日：1981-12-10

申请号：PCT/US1980000686

申请日：1980-06-02

申请人： MOSTEK CORP ,  MUELLER J ,  GILTNER M ,  FIEST R

发明人： MOSTEK CORP

IPC分类号： G06F03/04

CPC分类号： H03M7/42 ,  H04L9/0637 ,  H04L9/065 ,  H04L2209/30

摘要： In-line data compression system (10) which reduces the number of binary bits required to transmit a given text or similar message over a data network such a Telex or TWX. The unit (14) further provides an option for encrypting the compressed message. The unit (14) connected in-line between the local keyboard/printer terminal (12) and the network interface unit (16). The compression unit (14) can transmit or receive standard messages or can transmit compressed and encrypted messages to remote stations, and can receive, decrypt, and decompress messages from remote stations. The text data is compressed by identifying each word, searching for the word in a fixed library of words (38), and transmitting a first escape code plus the library address if the word is found. If the word is not found in the fixed library, a search is made for the word in a reconfiguration library (40) and a second escape code plus the reconfiguration library address is transmitted if the word is found. If the word is not found in the reconfiguration library, the word is transmitted one character at a time using variable length character codes produced by a "Huffman" type code generator. An identical unit (14) interposed at the receiving terminal but operating in the receiving mode can decrypt the message, then detect the escape codes and fetch words expressed in standard character codes from an identical fixed library (38) or an identically compiled reconfiguration library (40), or finally decodes the variable length character codes. The reconfiguration library is compiled by placing each word which is not in the library in the reconfiguration library before it is transmitted by variable length code. Then the second and each subsequent time that the same word is found in the message, the second escape code plus the address in the reconfiguration library will be transmitted in lieu of the Huffman coded characters of the word. The receiving station follows the same procedure on received messages to compile an identical reconfiguration library from which words previously in the messages can be outputted in response to a transmitted reconfiguration library escape code and address. The system is also applicable to compression of other types of data, serial or parallel, such as digital color television, for example.

摘要翻译： 在线数据压缩系统（10），其减少通过诸如电传或TWX的数据网络发送给定文本或类似消息所需的二进制位数。 单元（14）还提供用于加密压缩消息的选项。 在本地键盘/打印机终端（12）与网络接口单元（16）之间的线上连接的单元（14）。 压缩单元（14）可以发送或接收标准消息，或者可以将压缩和加密的消息发送到远程站，并且可以从远程站接收，解密和解压缩消息。 通过识别每个单词，在固定的单词库中搜索单词（38）来压缩文本数据，并且如果找到该单词，则发送第一个转义码加上库地址。 如果在固定库中没有找到该字，则在重配置库（40）中搜索该字，并且如果找到该字，则发送第二转义码加上重新配置库地址。 如果在重新配置库中没有找到该字，则使用由“霍夫曼”型代码生成器生成的可变长度字符代码，一次发送一个字符。 插入在接收终端但以接收模式操作的相同单元（14）可以对该消息进行解密，然后从相同的固定库（38）或相同编译的重新配置库（38）中检测出转义码并以标准字符代码表示的字， 40），或者最后解码可变长度字符代码。 通过将可变长度代码发送之前将不在库中的每个单词放在重新配置库中来编译重新配置库。 然后在消息中找到相同字的第二个和每个随后的时间，将发送第二转义码加上重新配置库中的地址来代替该字的霍夫曼编码字符。 接收站对接收到的消息遵循相同的过程以编译相同的重配置库，响应于所发送的重配置库转义码和地址，可以从其中输出先前在消息中的字。 该系统也适用于压缩其他类型的数据，串行或并行数据，例如数字彩色电视机。

公开(公告)号：WO1981002357A1

公开(公告)日：1981-08-20

申请号：PCT/US1981000148

申请日：1981-02-04

申请人： MOSTEK CORP

发明人： MOSTEK CORP ,  PARKINSON W

IPC分类号： G11C05/00

CPC分类号： G11C7/12 ,  G06F11/2015 ,  G11C5/141 ,  G11C5/146

摘要： A circuit for biasing the bit lines of a static semiconductor memory when each of the cells (150) within the memory is being powered by a backup power source due to failure of the primary power source. The bit lines (52) connected to the cells within the array (50) are connected to transistors (54) which bias the bit lines (52) to a high voltage upon detection of failure of the primary power for the computer. The bit lines (52) are maintained at a high voltage level to prevent discharge of a data storage node (156) through an access transistor (164) of a memory cell (150). Biasing of the bit lines (52) further prevents the integrated circuit substrate (150) from being driven excessively positive by capacitive coupling between the substrate (150) and the bit lines (52) when the primary power is restored to the circuit.

公开(公告)号：WO1981001778A1

公开(公告)日：1981-06-25

申请号：PCT/US1980000510

申请日：1980-05-05

申请人： MOSTEK CORP

发明人： MOSTEK CORP ,  YOUNG I

IPC分类号： H03F01/08

CPC分类号： H03H19/004

摘要： Switched-capacitor circuit (50) for passing an audio frequency over a predetermined range of frequencies fabricated on a monolithic semiconductor substrate. The switched-capacitor filter (50) includes a first amplifier (60) and a second amplifier (90). A first integrator capacitor (66) is interconnected to the first amplifier (60). A second integrator capacitor (96) is interconnected to the first amplifier (90). A first input switched-capacitor (82) is interconnected between the first amplifier (60) and the second amplifier (90), such that the first input switched-capacitor (82) samples and holds the output of the second amplifier (90) during a first clock phase thereby isolating the output of the second amplifier (90) from the input of the first amplifier (60). During a second clock phase the first input switched-capacitor (82) applies the output of the second amplifier (90) to the first integrator capacitor (66). A second input switched-capacitor (112) is provided and is interconnected between the output of the first amplifier (60) and the input of the second amplifier (90), such that during the second clock phase the second input switched-capacitor (112) applies the output of the first amplifier (60) to the second integrator capacitor (96). The switched-capacitor circuit (50) functions such that effectively zero phase shift is introduced into the signal being processed by the switched-capacitor circuit (50).

摘要翻译： 开关电容器电路（50），用于使音频频率超过制造在单片半导体衬底上的预定频率范围。 开关电容滤波器（50）包括第一放大器（60）和第二放大器（90）。 第一积分器电容器（66）互连到第一放大器（60）。 第二积分电容器（96）与第一放大器（90）互连。 第一输入开关电容器（82）在第一放大器（60）和第二放大器（90）之间互连，使得第一输入开关电容器（82）在第一输入开关电容器（82）的采样和保持第二放大器 第一时钟相位，从而将第二放大器（90）的输出与第一放大器（60）的输入隔离。 在第二时钟相位期间，第一输入开关电容器（82）将第二放大器（90）的输出施加到第一积分器电容器（66）。 提供第二输入开关电容器（112）并且在第一放大器（60）的输出端和第二放大器（90）的输入端之间互连，使得在第二时钟相位期间，第二输入开关电容器（112） ）将第一放大器（60）的输出施加到第二积分器电容器（96）。 开关电容器电路（50）的功能是使得有效的零相移被引入由开关电容器电路（50）处理的信号中。

公开(公告)号：WO1982004345A1

公开(公告)日：1982-12-09

申请号：PCT/US1981000705

申请日：1981-05-27

申请人： MOSTEK CORP ,  ASWELL CECIL JAMES

发明人： MOSTEK CORP

IPC分类号： G11C11/40

CPC分类号： G06F1/28 ,  G11C5/00 ,  G11C5/141 ,  Y10S331/03 ,  Y10T307/625

摘要： A power supply control circuit (20) selectively provides power to an integrated circuit from either a primary power supply terminal (22), or through terminals (24, 26) connected to backup batteries. The voltage level of the primary power is monitored continuously and when it drops to a predetermined level one of the two backup batteries is substituted to power the integrated circuit in a power-down mode. The circuit (20) includes a level detector circuit (32) and a voltage reference circuit (98). In the power-down mode one battery is connected to power the integrated circuit and this battery is continuously monitored. When the voltage of the on-line battery drops to below a fixed level in comparison to off-line battery a control logic circuit (92) activates switches (56) to substitute the off-line battery for the on-line battery. Control logic circuitry (92) is provided to disconnect the control signals from the integrated circuit to prevent loss of stored information. Further the failure of one of the backup batteries is indicated by disabling a write enable signal.

摘要翻译： 电源控制电路（20）从主电源端子（22）或连接到备用电池的端子（24,26）选择性地向集成电路提供电力。 一次电源的电压水平被连续监测，当它下降到预定水平时，两个备用电池中的一个替代以断电模式为集成电路供电。 电路（20）包括电平检测器电路（32）和电压参考电路（98）。 在掉电模式下，一个电池连接到集成电路供电，并持续监控该电池。 与离线电池相比，当在线电池的电压下降到低于固定电平时，控制逻辑电路（92）激活开关（56）以将离线电池替代为在线电池。 提供控制逻辑电路（92）以断开来自集成电路的控制信号，以防止存储信息的丢失。 此外，一个备用电池的故障通过禁用写使能信号来指示。