公开(公告)号：WO2009076531A3

公开(公告)日：2009-07-30

申请号：PCT/US2008086435

申请日：2008-12-11

Applicant: QUALCOMM INC ,  CODRESCU LUCIAN ,  PLONDKE ERICH J ,  VENKUMAHANTI SURESH K ,  AHMED MUHAMMAD ,  ANDERSON WILLIAM C

Inventor： CODRESCU LUCIAN ,  PLONDKE ERICH J ,  VENKUMAHANTI SURESH K ,  AHMED MUHAMMAD ,  ANDERSON WILLIAM C

IPC: G06F9/48

CPC classification number: G06F9/4812 ,  G06F9/30123 ,  G06F9/3013 ,  G06F9/3851

Abstract: A multi-threaded processor is disclosed that includes a sequencer adapted to provide instructions associated with one or more threads of a multi-threaded processor. The sequencer includes an interrupt controller adapted to receive one or more interrupts and to selectively allow a first thread of the one or more threads to service at least one interrupt. The interrupt controller includes logic to preclude a second thread of the one or more threads from responding to the at least one interrupt.

Abstract translation: 公开了一种多线程处理器，其包括适用于提供与多线程处理器的一个或多个线程相关联的指令的定序器。 定序器包括适于接收一个或多个中断并且选择性地允许一个或多个线程中的第一线程服务于至少一个中断的中断控制器。 中断控制器包括用于排除一个或多个线程中的第二线程对至少一个中断作出响应的逻辑。

公开(公告)号：WO2006110886A3

公开(公告)日：2007-03-29

申请号：PCT/US2006013948

申请日：2006-04-11

Applicant: QUALCOMM INC ,  AHMED MUHAMMAD ,  CODRESCU LUCIAN ,  PLONDKE ERICH ,  ANDERSON WILLIAM C ,  LESTER ROBERT ALLAN ,  JONES PHILLIP M

Inventor： AHMED MUHAMMAD ,  CODRESCU LUCIAN ,  PLONDKE ERICH ,  ANDERSON WILLIAM C ,  LESTER ROBERT ALLAN ,  JONES PHILLIP M

IPC: G06F9/38

CPC classification number: G06F9/325 ,  G06F9/3802 ,  G06F9/3804 ,  G06F9/381

Abstract: An instruction memory unit comprises a first memory structure operable to store program instructions, and a second memory structure operable to store program instructions fetched from the first memory structure, and to issue stored program instructions for execution. The second memory structure is operable to identify a repeated issuance of a forward program redirect construct, and issue a next program instruction already stored in the second memory structure if a resolution of the forward branching instruction is identical to a last resolution of the same. The second memory structure is further operable to issue a backward program redirect construct, determine whether a target instruction is stored in the second memory structure, issue the target instruction if the target instruction is stored in the second memory structure, and fetch the target instruction from the first memory structure if the target instruction is not stored in the second memory structure.

Abstract translation: 指令存储器单元包括可操作以存储程序指令的第一存储器结构，以及可操作以存储从第一存储器结构提取的程序指令的第二存储器结构，以及发出用于执行的存储的程序指令。 如果前向分支指令的分辨率与其最后一个分辨率相同，则第二存储器结构可操作以识别前向程序重定向构造的重复发出，并且发出已经存储在第二存储器结构中的下一个程序指令。 第二存储器结构进一步可操作以发出反向程序重定向结构，确定目标指令是否存储在第二存储器结构中，如果目标指令存储在第二存储器结构中，则发出目标指令，并从 如果目标指令未被存储在第二存储器结构中的第一存储器结构。

公开(公告)号：WO2007056675A2

公开(公告)日：2007-05-18

申请号：PCT/US2006060500

申请日：2006-11-02

Applicant: QUALCOMM INC ,  AHMED MUHAMMAD ,  INGLE AJAY ANANT ,  JAMIL SUJAT

Inventor： AHMED MUHAMMAD ,  INGLE AJAY ANANT ,  JAMIL SUJAT

CPC classification number: G06F9/30181 ,  G06F9/30032 ,  G06F9/3012 ,  G06F9/30189 ,  G06F9/3802 ,  G06F9/3851 ,  G06F9/3885

Abstract: An arithmetic logic and shifting device is disclosed and includes an arithmetic logic unit that has a first input to receive a first operand from a first register port, a second input to receive a second operand from a second register port, and an output to selectively provide a memory address to a memory unit in a first mode of operation and to selectively provide an arithmetic output in a second mode of operation. Further, the arithmetic logic and shifting device includes a programmable shifter device that has a first input to receive data from the memory unit, a second input to receive the arithmetic output, a third input to receive an operation code of a computer execution instruction, and a shifted output to provide shifted data.

Abstract translation: 公开了算术逻辑和移位装置，并且包括算术逻辑单元，该算术逻辑单元具有从第一寄存器端口接收第一操作数的第一输入端，从第二寄存器端口接收第二操作数的第二输入端和选择性地提供 以第一操作模式向存储器单元提供存储器地址，并且在第二操作模式中选择性地提供算术输出。 此外，算术逻辑和移位装置包括可编程移位器装置，其具有用于从存储器单元接收数据的第一输入端，用于接收算术输出的第二输入端，用于接收计算机执行指令的操作码的第三输入端，以及 移位输出以提供移位数据。

公开(公告)号：WO2006099584A3

公开(公告)日：2007-03-01

申请号：PCT/US2006009782

申请日：2006-03-14

Applicant: QUALCOMM INC ,  JAMIL SUJAT ,  PLONDKE ERICH ,  CODRESCU LUCIAN ,  AHMED MUHAMMAD ,  ANDERSON WILLIAM C

Inventor： JAMIL SUJAT ,  PLONDKE ERICH ,  CODRESCU LUCIAN ,  AHMED MUHAMMAD ,  ANDERSON WILLIAM C

IPC: G06F9/38

CPC classification number: G06F9/3851

Abstract: Techniques for processing transmissions in a communications (e.g., CDMA) system. A multithreaded processor processes a plurality of threads operating via a plurality of processor pipelines associated with the multithreaded processor and predetermines a triggering event for the multithreaded processor to switch from a first thread to a second thread. The triggering event is variably and dynamically determined to optimize multithreaded processor performance. The triggering event may be a dynamically determined number of processor cycles, the number being determined to optimize the performance of the multithreaded processor, or a variably and dynamically determined event, such as a cache or instruction miss.

Abstract translation: 用于在通信（例如，CDMA）系统中处理传输的技术。 多线程处理器处理通过与多线程处理器相关联的多个处理器管线操作的多个线程，并且预先确定用于多线程处理器从第一线程切换到第二线程的触发事件。 触发事件是可变和动态的，以优化多线程处理器性能。 触发事件可以是动态确定的处理器周期数，被确定为优化多线程处理器的性能的数量，或可变和动态确定的事件，例如高速缓存或指令未命中。

公开(公告)号：WO2007048133A3

公开(公告)日：2007-08-02

申请号：PCT/US2006060133

申请日：2006-10-20

Applicant: QUALCOMM INC ,  PLONDKE ERICH ,  CODRESCU LUCIAN ,  AHMED MUHAMMAD ,  ZENG MAO ,  JAMIL SUJAT ,  ANDERSON WILLIAM C

Inventor： PLONDKE ERICH ,  CODRESCU LUCIAN ,  AHMED MUHAMMAD ,  ZENG MAO ,  JAMIL SUJAT ,  ANDERSON WILLIAM C

IPC: G06F9/355 ,  G06F5/06

CPC classification number: G06F5/10 ,  G06F9/3552 ,  G06F9/3851 ,  G06F2205/106

Abstract: Techniques for processing digital signals for a variety of applications, including in a communications (e.g. , CDMA) system. A pointer location within a circular buffer is determined by establishing a length of the circular buffer, a start address that is aligned to a power of 2, and an end address located distant from the start address by the length and less than a power of 2 greater than the length. The method and system determine a current pointer location for an address within the circular buffer, a stride value of bits between the start address and the end address, a new pointer location within the circular buffer by adding the current pointer location to the stride value. An adjusted pointer location is within the circular buffer by an arithmetic operation of the new pointer location with the length.

Abstract translation: 用于处理包括在通信（例如CDMA）系统中的各种应用的数字信号的技术。 循环缓冲器中的指针位置通过建立循环缓冲器的长度，与2的幂对齐的起始地址和远离起始地址长度并小于2的幂的结束地址来确定 大于长度。 该方法和系统确定循环缓冲器内的地址的当前指针位置，起始地址和结束地址之间的比特的步幅值，通过将当前指针位置添加到步幅值，循环缓冲器内的新指针位置。 通过具有长度的新指针位置的算术运算，调整的指针位置在循环缓冲器内。

公开(公告)号：WO2006110906A3

公开(公告)日：2007-07-26

申请号：PCT/US2006014174

申请日：2006-04-11

Applicant: QUALCOMM INC ,  CODRESCU LUCIAN ,  PLONDKE ERICH ,  AHMED MUHAMMAD ,  ANDERSON WILLIAM C ,  SIMPSON TAYLOR

Inventor： CODRESCU LUCIAN ,  PLONDKE ERICH ,  AHMED MUHAMMAD ,  ANDERSON WILLIAM C ,  SIMPSON TAYLOR

IPC: G06F9/30 ,  G06F9/38

CPC classification number: H04M1/72522 ,  G06F9/3012 ,  G06F9/3885 ,  H04M1/2535 ,  H04M2250/02

Abstract: A processor device is disclosed and includes a memory and a sequencer that is responsive to the memory. The sequencer can support very long instruction word (VLIW) instructions and superscalar instructions. The processor device further includes a first instruction execution unit responsive to the sequencer, a second instruction execution unit responsive to the sequencer, a third instruction execution unit responsive to the sequencer, and a fourth instruction execution unit responsive to the sequencer. Further, the processor device includes a plurality of register files and each of the plurality of register files includes a plurality of registers. The plurality of register files are coupled to the sequencer and coupled to the first instruction execution unit, the second instruction execution unit, the third instruction execution unit, and the fourth instruction execution unit.

Abstract translation: 公开了处理器设备，并且包括响应于存储器的存储器和定序器。 定序器可以支持非常长的指令字（VLIW）指令和超标量指令。 处理器装置还包括响应于定序器的第一指令执行单元，响应于定序器的第二指令执行单元，响应于定序器的第三指令执行单元，以及响应于定序器的第四指令执行单元。 此外，处理器装置包括多个寄存器文件，并且多个寄存器文件中的每一个包括多个寄存器。 多个寄存器文件耦合到定序器并耦合到第一指令执行单元，第二指令执行单元，第三指令执行单元和第四指令执行单元。

公开(公告)号：WO2006105295A2

公开(公告)日：2006-10-05

申请号：PCT/US2006011646

申请日：2006-03-28

Applicant: QUALCOMM INC ,  AHMED MUHAMMAD ,  PLONDKE ERICH ,  CODRESCU LUCIAN ,  ANDERSON WILLIAM C

Inventor： AHMED MUHAMMAD ,  PLONDKE ERICH ,  CODRESCU LUCIAN ,  ANDERSON WILLIAM C

IPC: G06F9/38

CPC classification number: G06F9/3853 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3857

Abstract: Techniques for processing transmissions in a communications (e.g., CDMA) system. A method and system for issuing and executing mixed architecture instructions in a multiple-issue digital signal processor receives in a mixed instruction listing a plurality of digital signal processor instructions. The plurality of digital signal processor instructions includes a plurality of parallel executable instructions (e.g., VLIW instructions or instruction packets) mixed among a plurality of series executable instructions (e.g., superscalar instructions). The series executable instructions are associated by various instruction dependencies. The method and system further identify in the mixed instruction listing the plurality of parallel executable instructions. Once identified, the parallel executable instructions are first executed in parallel irrespective of any such instruction's relative order in the mixed instruction listing. Then, the series executable instructions are executed serially according to said various instruction dependencies.

Abstract translation: 用于在通信（例如，CDMA）系统中处理传输的技术。 用于在多问题数字信号处理器中发出和执行混合架构指令的方法和系统以列出多个数字信号处理器指令的混合指令接收。 多个数字信号处理器指令包括在多个串行可执行指令（例如，超标量指令）中混合的多个并行可执行指令（例如，VLIW指令或指令分组）。 该系列可执行指令通过各种指令依赖关联。 该方法和系统进一步标识列出多个并行可执行指令的混合指令。 一旦确定，并行执行并行执行指令，而不管混合指令列表中的这种指令的相对顺序如何。 然后，根据所述各种指令依赖性，串行执行指令被串行执行。

公开(公告)号：WO2006128079A3

公开(公告)日：2007-02-08

申请号：PCT/US2006020640

申请日：2006-05-25

Applicant: QUALCOMM INC ,  MOHAMMAD BAKER ,  AHMED MUHAMMAD ,  BASSETT PAUL ,  JAMIL SUJAT ,  INGLE AJAY ANANT

Inventor： MOHAMMAD BAKER ,  AHMED MUHAMMAD ,  BASSETT PAUL ,  JAMIL SUJAT ,  INGLE AJAY ANANT

IPC: G06F12/08 ,  G11C15/04

CPC classification number: G06F12/0895 ,  G06F12/0864 ,  G06F12/0893

Abstract: Techniques for processing transmissions in a communications (e.g., CDMA) system including the use of a digital signal processor. The digital signal processor includes a cache memory system and associates a plurality of cache memory match lines with addressable memory lines of an addressable memory. Each of the cache memory match lines associates with one of corresponding sets of the cache memory. The method and system maintain each of the cache memory match lines at a low voltage. Once the digital signal processor initiates a search of the cache memory for retrieving data from a selected one of the corresponding sets of the cache memory, a match line drive circuit drives one of the cache memory match lines from a low voltage to a high voltage. The selected one of the cache memory match lines corresponds to the selected one of the corresponding sets of the cache memory. The digital signal processor compares the selected one of the cache memory match lines to an associated one of the addressable memory lines. Following the comparison step, the process returns the one of the cache memory match lines to the low voltage.

Abstract translation: 用于处理包括使用数字信号处理器的通信（例如，CDMA）系统中的传输的技术。 数字信号处理器包括高速缓冲存储器系统，并将多个高速缓存存储器匹配线与可寻址存储器的可寻址存储器线相关联。 每个高速缓存存储器匹配行与高速缓冲存储器的相应组中的一个相关联。 该方法和系统将每个高速缓冲存储器匹配线保持在低电压。 一旦数字信号处理器启动对高速缓冲存储器的搜索，以从相应的高速缓冲存储器组中的选定的一个中选出一个数据，则匹配线驱动电路将高速缓冲存储器匹配线之一从低电压驱动到高电压。 高速缓存存储器匹配行中所选择的一个对应于高速缓冲存储器的所选择的相应组中的一个。 数字信号处理器将所选择的一个高速缓冲存储器匹配线与可寻址存储器线中的相关联的一个进行比较。 在比较步骤之后，该过程将高速缓存存储器匹配行之一返回到低电压。

公开(公告)号：WO2006116257A2

公开(公告)日：2006-11-02

申请号：PCT/US2006015390

申请日：2006-04-24

Applicant: QUALCOMM INC ,  CODRESCU LUCIAN ,  PLONDKE ERICH ,  AHMED MUHAMMAD ,  ANDERSON WILLIAM C

Inventor： CODRESCU LUCIAN ,  PLONDKE ERICH ,  AHMED MUHAMMAD ,  ANDERSON WILLIAM C

IPC: G06F9/38

CPC classification number: G06F9/3851 ,  G06F9/3853

Abstract: A multithreaded processor device is disclosed and includes a first program thread and second program thread. The second program thread is execution linked to the first program thread in a lock step manner. As such, when the first program thread experiences a stall event, the second program thread is instructed to perform a no operation instruction in order to keep the second program thread execution linked to the first program thread. Also, the second program thread performs a no operation instruction during each clock cycle that the first program thread is stalled due to the stall event. When the first program thread performs a first successful operation after the stall event, the second program thread restarts normal execution.

Abstract translation: 公开了一种多线程处理器设备，并且包括第一程序线程和第二程序线程。 第二个程序线程以锁定步骤的方式执行链接到第一个程序线程。 这样，当第一程序线程经历停顿事件时，指示第二程序线程执行无操作指令，以便使第二程序线程执行与第一程序线程相关联。 此外，第二程序线程在每个时钟周期期间执行无操作指令，由于失速事件使第一程序线程停滞。 当第一程序线程在停止事件之后执行第一次成功操作时，第二程序线程重新启动正常执行。

公开(公告)号：WO2006110905A2

公开(公告)日：2006-10-19

申请号：PCT/US2006014173

申请日：2006-04-11

Applicant: QUALCOMM INC ,  AHMED MUHAMMAD ,  PLONDKE ERICH ,  CODRESCU LUCIAN ,  ANDERSON WILLIAM C

Inventor： AHMED MUHAMMAD ,  PLONDKE ERICH ,  CODRESCU LUCIAN ,  ANDERSON WILLIAM C

CPC classification number: G06F9/3842 ,  G06F9/3851 ,  G06F9/3885

Abstract: A processor device is disclosed and includes a memory unit and at least one interleaved multi-threading instruction pipeline. The interleaved multi-threading instruction pipeline utilizes a number of clock cycles that is less than an instruction issue rate for each of a plurality of program threads that are stored within the memory unit. The memory unit includes six instruction caches. Further, the processor device includes six register files and each of the six register files is associated with one of the six instruction caches. Each of the plurality of program threads is associated with one of the six register files. Further, each of the six program threads includes a plurality of instructions and each of the plurality of instructions is stored within one of the six instruction caches of the memory.

Abstract translation: 公开了一种处理器设备，并且包括存储器单元和至少一个交错多线程指令流水线。 交错多线程指令流水线利用了小于存储在存储器单元内的多个程序线程中的每一个的指令发布速率的多个时钟周期。 存储单元包括六个指令高速缓存。 此外，处理器设备包括六个寄存器文件，六个寄存器文件中的每一个与六个指令高速缓存中的一个相关联。 多个程序线程中的每一个与六个寄存器文件之一相关联。 此外，六个程序线程中的每一个包括多个指令，并且多个指令中的每一个被存储在存储器的六个指令高速缓存之一中。