公开(公告)号：WO2021167209A1

公开(公告)日：2021-08-26

申请号：PCT/KR2020/016606

申请日：2020-11-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUH, Dongkwan ,  LEE, Jonghun

IPC: G06F9/355 ,  G06F9/30 ,  G06F9/38

Abstract: An electronic device and a control method thereof are disclosed. The electronic device includes: a memory storing input data, and a processor including a first register file and a second register file storing index data corresponding to kernel data, wherein the processor is configured to: based on a first command being input, obtain offset information of valid data included in a part of the index data stored in the first register file, based on the number of pieces of the offset information being greater than or equal to a predetermined number, store data packed with the offset information in a unit of the predetermined number in the second register file, and obtain output data by performing an operation regarding the input data based on the packed data.

公开(公告)号：WO2020236370A1

公开(公告)日：2020-11-26

申请号：PCT/US2020/028806

申请日：2020-04-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： WALLACH, Steven, Jeffrey

IPC: G06F9/30 ,  G06F9/355 ,  G06F9/38 ,  G06F15/80

Abstract: Disclosed herein are vector index registers for storing or loading indexes of true and/or false results of conditional operations using multiple lane processing in vector processors. Each of the vector index registers store multiple addresses for accessing multiple positions in operand vectors in various types of operations that can leverage multi-lane processing.

公开(公告)号：WO2020236369A1

公开(公告)日：2020-11-26

申请号：PCT/US2020/028805

申请日：2020-04-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： WALLACH, Steven, Jeffrey

IPC: G06F9/30 ,  G06F9/355 ,  G06F15/80

Abstract: Disclosed herein are vector index registers for storing or loading indexes of true and/or false results of conditional operations in vector processors. Each of the vector index registers store multiple addresses for accessing multiple positions in operand vectors in various types of operations.

公开(公告)号：WO2019102662A1

公开(公告)日：2019-05-31

申请号：PCT/JP2018/030256

申请日：2018-08-14

Applicant: ソニーセミコンダクタソリューションズ株式会社

Inventor： 小林　浩

IPC: G06F9/30 ,  G06F9/318 ,  G06F9/355

CPC classification number: G06F9/30 ,  G06F9/34 ,  G06F9/355

Abstract: フェッチされた命令の所定のフィールドを拡張して、命令の種類やオペランドの長さを確保する。　命令変換テーブルは、命令の所定のフィールドのビットパターンに関連付けて前記所定のフィールドより長い拡張フィールドを記憶する。拡張フィールド取得部は、フェッチされた命令の所定のフィールドのビットパターンによって命令変換テーブルを参照して、拡張フィールドを取得する。命令デコーダは、フェッチされた命令の所定のフィールドに代えて拡張フィールドを備える新たな命令について、デコード処理を行う。

公开(公告)号：WO2016171866A1

公开(公告)日：2016-10-27

申请号：PCT/US2016/025279

申请日：2016-03-31

Applicant: OPTIMUM SEMICONDUCTOR TECHNOLOGIES, INC.

Inventor： MOUDGILL, Mayan ,  NACER, Gary ,  GLOSSNER, C., John ,  HOANE, A., Joseph ,  HURTLEY, Paul ,  MURUGAPPAN, Senthilvelan ,  BALZOLA, Pablo

IPC: G06F9/355

CPC classification number: G06F9/30029 ,  G06F3/0604 ,  G06F3/0647 ,  G06F3/0673 ,  G06F9/30 ,  G06F9/30032 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/30054 ,  G06F9/30058 ,  G06F9/3013 ,  G06F9/322 ,  G06F9/355 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0893 ,  G06F12/1009 ,  G06F2212/452 ,  G06F2212/60 ,  G06F2212/602

Abstract: A computer processor with an address register file is disclosed. The computer processor may include a memory. The computer processor may further include a general purpose register file comprising at least one general purpose register. The computer processor may further include an address register file comprising at least one address register. The computer processor may further include having access to the memory, the general purpose register file, and the address register file. The processing logic may execute a memory access instruction that accesses one or more memory locations in the memory at one or more corresponding addresses computed by retrieving the value of an address register of the at least one register of the address register file specified in the instruction and adding a displacement value encoded in the instruction.

Abstract translation: 公开了一种具有地址寄存器文件的计算机处理器。 计算机处理器可以包括存储器。 计算机处理器还可以包括包括至少一个通用寄存器的通用寄存器文件。 计算机处理器还可以包括包括至少一个地址寄存器的地址寄存器文件。 计算机处理器还可以包括访问存储器，通用寄存器文件和地址寄存器文件。 处理逻辑可以执行存储器访问指令，该存储器访问指令通过检索指令中指定的地址寄存器文件的至少一个寄存器的地址寄存器的值而计算的一个或多个对应地址访问存储器中的一个或多个存储器位置，以及 添加在指令中编码的位移值。

公开(公告)号：WO2012120267A1

公开(公告)日：2012-09-13

申请号：PCT/GB2012/050158

申请日：2012-01-26

Applicant: ARM LIMITED ,  STEPHENS, Nigel John ,  SEAL, David James

Inventor： STEPHENS, Nigel John ,  SEAL, David James

IPC: G06F9/34 ,  G06F9/30 ,  G06F9/32 ,  G06F9/355

CPC classification number: G06F9/3557 ,  G06F9/30007 ,  G06F9/30112 ,  G06F9/30167 ,  G06F9/342 ,  G06F9/345 ,  G06F2212/657

Abstract: A data processing apparatus is provided comprising processing circuitry and an instruction decoder responsive to program instructions to control processing circuitry to perform the data processing. The instruction decoder is responsive to an address calculating instruction to perform an address calculating operation for calculating a partial address result from a non-fixed reference address and a partial offset value such that a full address specifying a memory location of an information entity is calculable from said partial address result using at least one supplementary program instruction. The partial offset value has a bit-width greater than or equal to said instruction size and is encoded within at least one partial offset field of said address calculating instruction. A corresponding data processing method, virtual machine and computer program product are also provided.

Abstract translation: 提供了一种数据处理装置，其包括响应于程序指令的处理电路和指令解码器，以控制处理电路执行数据处理。 指令解码器响应于地址计算指令来执行地址计算操作，用于从非固定参考地址和部分偏移值计算部分地址结果，使得可以从...计算指定信息实体的存储位置的完整地址 所述部分地址结果使用至少一个补充程序指令。 部分偏移值具有大于或等于所述指令大小的位宽，并且被编码在所述地址计算指令的至少一个部分偏移字段内。 还提供了相应的数据处理方法，虚拟机和计算机程序产品。

公开(公告)号：WO2009136043A3

公开(公告)日：2010-08-19

申请号：PCT/FR2009050574

申请日：2009-04-03

Applicant: ALVEOL TECHNOLOGY SARL ,  JACHIET FREDERIC

Inventor： JACHIET FREDERIC

IPC: G06F9/38 ,  G06F9/34 ,  G06F9/355

CPC classification number: G06F12/0284 ,  G06F11/3636 ,  G06F12/10 ,  G06F12/145 ,  Y02D10/13

Abstract: The invention relates to a method of creating a virtual address for a so-called "daughter" software entity belonging to the context of a so-called "mother" software entity, this virtual address (3.0.1) comprising a series of fields (3.0) making it possible to retrieve the series of fields (3.0) of the virtual address of the mother software entity and a unique field (1) in the context of the mother software entity, and in which each series of fields is associated with a single software entity that it defines fully.

Abstract translation: 本发明涉及一种为属于所谓“母”软件实体的上下文的所谓“女儿”软件实体创建虚拟地址的方法，该虚拟地址（3.0.1）包括一系列字段（ 3.0）使得可以在母版软件实体的上下文中检索母系软件实体的虚拟地址的一系列字段（3.0）和唯一字段（1），并且其中每一系列字段与 它完全定义的单一软件实体。

公开(公告)号：WO2009067598A1

公开(公告)日：2009-05-28

申请号：PCT/US2008/084189

申请日：2008-11-20

Applicant: QUALCOMM Incorporated ,  KRITHIVASAN, Shankar ,  ZENG, Mao ,  CODRESCU, Lucian ,  PLONDKE, Erich J.

Inventor： KRITHIVASAN, Shankar ,  ZENG, Mao ,  CODRESCU, Lucian ,  PLONDKE, Erich J.

IPC: G06F9/30 ,  G06F9/355 ,  G06F9/315

CPC classification number: G06F9/3555 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/3004

Abstract: In a particular embodiment, a method is disclosed that includes executing a single instruction to identify a location within a table stored at a memory. The single instruction is executable by a processor to extract bit field data from a first register and insert the bit field data into an index portion of a second register. The second register includes a table address portion and an index portion. The table address portion includes a table address identifying a memory location associated with a table. The table address and the bit field data combine to form an indexed address to an element within the table.

Abstract translation: 在特定实施例中，公开了一种方法，其包括执行单个指令以识别存储在存储器中的表中的位置。 单个指令可由处理器执行以从第一寄存器提取位字段数据，并将位字段数据插入第二寄存器的索引部分。 第二寄存器包括表地址部分和索引部分。 表地址部分包括标识与表相关联的存储器位置的表地址。 表地址和位字段数据组合起来，形成一个索引地址给表中的一个元素。

公开(公告)号：WO2007048133A2

公开(公告)日：2007-04-26

申请号：PCT/US2006/060133

申请日：2006-10-20

Applicant: QUALCOMM INCORPORATED ,  PLONDKE, Erich ,  CODRESCU, Lucian ,  AHMED, Muhammad ,  ZENG, Mao ,  JAMIL, Sujat ,  ANDERSON, William, C.

Inventor： PLONDKE, Erich ,  CODRESCU, Lucian ,  AHMED, Muhammad ,  ZENG, Mao ,  JAMIL, Sujat ,  ANDERSON, William, C.

IPC: G06F9/355

CPC classification number: G06F5/10 ,  G06F9/3552 ,  G06F9/3851 ,  G06F2205/106

Abstract: Techniques for processing digital signals for a variety of applications, including in a communications (e.g., CDMA) system. A pointer location within a circular buffer is determined by establishing a length of the circular buffer, a start address that is aligned to a power of 2, and an end address located distant from the start address by the length and less than a power of 2 greater than the length. The method and system determine a current pointer location for an address within the circular buffer, a stride value of bits between the start address and the end address, a new pointer location within the circular buffer that is shifted from the current pointer location by the number of bits of the stride value. An adjusted pointer location is within the circular buffer by an arithmetic operation of the new pointer location with the length.

Abstract translation: 用于处理各种应用的数字信号的技术，包括在通信（例如CDMA）系统中。 循环缓冲器中的指针位置通过建立循环缓冲器的长度，与2的幂对齐的起始地址以及远离起始地址长度而小于2的幂的结束地址来确定 大于长度。 方法和系统确定循环缓冲区内的地址的当前指针位置，起始地址和结束地址之间的比特的步幅值，循环缓冲区内的新指针位置，从当前指针位置移位数字 的步幅值。 通过具有长度的新指针位置的算术运算，调整的指针位置在循环缓冲器内。

公开(公告)号：WO03093981A2

公开(公告)日：2003-11-13

申请号：PCT/IB0301701

申请日：2003-04-22

Applicant: KONINKL PHILIPS ELECTRONICS NV

Inventor： VAN DE WAERDT JAN-WILLEM

IPC: G06F9/38 ,  G06F12/02 ,  G06F12/08 ,  G06F9/355

CPC classification number: G06F12/0862 ,  G06F2212/6028

Abstract: As microprocessor speeds increase, processor performance is more and more affected by data access operations. When a processor, in operation, needs to await data due to slow data retrieval times, this is termed a processor stall and, in quantitative terms is referred to as processor stall cycles. As would be anticipated, pre-fetching of data from RAM memory is performed to reduce processor stall cycles, where a goal of pre-fetching in a processor-based system is to reduce a processing time penalty incurred during the processor stall cycle. Providing a combined solution of hardware and software directed pre-fetching is the most advantageous since: instruction bandwidth is not compromised, by limiting an amount of additional instructions in a program stream, and an additional amount of hardware resources is minimized. Instead of trying to detect regularity in memory references by hardware or software, as is taught in the prior art, the hardware and software directed pre-fetching technique is performed without explicit pre-fetch instructions utilized within the program stream and occupies a minimal amount of additional chip area. In order to minimize instruction bandwidth of the processor, the software and hardware directed pre-fetching approach uses additional registers located at an architectural level of the processor in order to specify pre-fetch regions, and a respective stride to be used for each of the regions. Advantageously, the impact to the instruction bandwidth of processing of instructions by the processor is limited to those additional instructions contained within the application that are required to set these registers. Where a frequency of pre-fetches is controlled using a spacing of memory access instructions contained within the application.

Abstract translation: 随着微处理器速度的提高，处理器性能受数据访问操作的影响越来越大。 当操作中的处理器由于数据检索时间慢而需要等待数据时，这被称为处理器停顿，并且在定量方面被称为处理器失速周期。 如预期的那样，执行从RAM存储器中预取数据以减少处理器停顿周期，其中在基于处理器的系统中预取的目标是减少在处理器停止周期期间产生的处理时间损失。 提供硬件和软件定向预取的组合解决方案是最有利的，因为：通过限制程序流中的附加指令量，指令带宽不受损害，并且额外的硬件资源量被最小化。 如现有技术中所教导的，不是尝试通过硬件或软件来检测存储器引用的规律性，而是在程序流内使用没有明确的预取指令的情况下执行硬件和软件定向预取技术，并且占用最小量的 额外的芯片面积。 为了最小化处理器的指令带宽，软件和硬件定向预取方法使用位于处理器的架构级别的附加寄存器，以便指定预取区域，以及用于每个 区域。 有利的是，处理器对处理指令的指令带宽的影响限于设置这些寄存器所需的应用程序中包含的附加指令。 在使用包含在应用程序内的存储器访问指令的间隔来控制预取的频率的地方。