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    MULTI-STAGE SWITCHED-CAPACITOR DC BLOCKING CIRCUIT FOR AUDIO FRONTEND
    2.
    发明申请
    MULTI-STAGE SWITCHED-CAPACITOR DC BLOCKING CIRCUIT FOR AUDIO FRONTEND 审中-公开
    用于音频保护的多级开关电容直流阻塞电路

    公开(公告)号：WO2015153025A1

    公开(公告)日：2015-10-08

    申请号：PCT/US2015/017697

    申请日：2015-02-26

    Applicant: QUALCOMM INCORPORATED

    Inventor： AZIN, Meysam ,  MEHRABI, Arash ,  HUANG, Wenchang

    IPC: H03F3/00 ,  H03F3/181 ,  H03F3/187 ,  H03H19/00

    CPC classification number: H03F3/185 ,  H03F3/005 ,  H03F3/181 ,  H03F3/187 ,  H03F3/45179 ,  H03F3/45183 ,  H03F2200/03 ,  H03F2203/45016 ,  H03F2203/45514 ,  H03H19/004 ,  H04R3/00

    Abstract: An integrated DC blocking amplifier circuit (100), including: an operational amplifier (110) configured in a differential amplifier; and at least first and second two-stage switched-capacitor circuits, each two stage switched-capacitor circuit including a first-stage circuit(140,144) and a second-stage circuit (142,146), wherein the first two-stage switched capacitor circuit is connected to a positive feedback path of the operational amplifier and the second two-stage switched capacitor circuit is connected to a negative feedback path of the operational amplifier, wherein the first-stage circuit is switched at a relatively low switching frequency, while the second-stage circuit is switched at a relatively high switching frequency.

    Abstract translation: 一种集成直流阻塞放大器电路（100），包括：配置在差分放大器中的运算放大器（110） 以及至少第一和第二两级开关电容器电路，每个两级开关电容器电路包括第一级电路（140,144）和第二级电路（142,146），其中所述第一两级开关电容器电路是 连接到运算放大器的正反馈路径，并且第二两级开关电容器电路连接到运算放大器的负反馈路径，其中第一级电路以相对低的开关频率切换， 以较高的开关频率切换。

    LOW DISTORTION SAMPLE AND HOLD SWITCH
    3.
    发明申请
    LOW DISTORTION SAMPLE AND HOLD SWITCH 审中-公开
    低失真样品和保持开关

    公开(公告)号：WO2017052892A1

    公开(公告)日：2017-03-30

    申请号：PCT/US2016/048143

    申请日：2016-08-23

    Applicant: QUALCOMM INCORPORATED

    Inventor： HU, Weibo ,  HUANG, Wenchang

    IPC: G11C27/02

    CPC classification number: H03M1/1245 ,  G11C27/024 ,  G11C27/026

    Abstract: Devices and methods for analog to digital conversion are provided. The device can have a supply voltage coupled to a bootstrap circuit operable to provide a boosted voltage during a first period defined by a sample phase (Ps) signal and a hold phase (Ph) signal. The device can also have a sampling circuit having an input node and operable to sample an input signal supplied to the input node. The device can also have a switching circuit having a first switch and a second switch. The switching circuit can be coupled to the bootstrap circuit and to the sampling circuit. The switching circuit can be configured to isolate the input node from shorting currents to the supply voltage for a portion of the first period.

    Abstract translation: 提供了模数转换的设备和方法。 该装置可以具有耦合到自举电路的电源电压，该自举电路可操作以在由采样相位（Ps）信号和保持相位（Ph）信号定义的第一周期期间提供升压电压。 该装置还可以具有具有输入节点的采样电路，并且可操作以对提供给输入节点的输入信号进行采样。 该装置还可以具有具有第一开关和第二开关的开关电路。 开关电路可以耦合到自举电路和采样电路。 开关电路可以被配置为在第一周期的一部分期间将输入节点与短路电流隔离到电源电压。

    COMMON-MODE COMPENSATION TECHNIQUE FOR PROGRAMMABLE GAIN AMPLIFIERS
    5.
    发明申请
    COMMON-MODE COMPENSATION TECHNIQUE FOR PROGRAMMABLE GAIN AMPLIFIERS 审中-公开
    可编程增益放大器的共模补偿技术

    公开(公告)号：WO2017034734A1

    公开(公告)日：2017-03-02

    申请号：PCT/US2016/044064

    申请日：2016-07-26

    Applicant: QUALCOMM INCORPORATED

    Inventor： KANAGAL RAMESH, Srinidhi Koushik ,  HUANG, Wenchang ,  AZIN, Meysam

    IPC: H03F3/30 ,  H03F3/45

    CPC classification number: H03G3/3005 ,  H03F1/0272 ,  H03F1/48 ,  H03F3/185 ,  H03F3/3011 ,  H03F3/45475 ,  H03F3/45941 ,  H03F2200/03 ,  H03F2200/36 ,  H03F2203/30031 ,  H03F2203/45074 ,  H03F2203/45082 ,  H03F2203/45418 ,  H03F2203/45424 ,  H03F2203/45434 ,  H03F2203/45512 ,  H03F2203/45528 ,  H03F2203/45534 ,  H03F2203/45536 ,  H03F2203/45544 ,  H03G3/001 ,  H03G5/28

    Abstract: Certain aspects of the present disclosure provide methods and apparatus for adjusting a bandwidth of an amplifier (e.g., a programmable gain amplifier (PGA)). In certain aspects, the PGA generally includes at least one amplification stage (320) having an input (301) and an output (303), a plurality of compensation capacitors (C c0 , C c1 , C c2 ) and at least one first switch (304, 306) configured to selectively couple at least one capacitor of the plurality of compensation capacitors between the input and the output of the at least one amplification stage. The amplifier includes at least one second switch (308, 310) configured to selectively couple the at least one capacitor to a node (CM sense) such that the at least one capacitor is coupled to only one of the output or the node, where a voltage at the node is a differential mode (DM) reference potential for the amplification stage.

    Abstract translation: 本公开的某些方面提供了用于调整放大器（例如，可编程增益放大器（PGA））的带宽的方法和装置。 在某些方面，PGA通常包括至少一个具有输入（301）和输出（303）的放大级（320），多个补偿电容器（Cc0，Cc1，Cc2）和至少一个第一开关（304， 306），被配置为在所述至少一个放大级的输入和输出之间选择性地耦合所述多个补偿电容器中的至少一个电容器。 放大器包括被配置为选择性地将至少一个电容器耦合到节点（CM sense）的至少一个第二开关（308,310），使得至少一个电容器仅耦合到输出或节点中的一个，其中a 节点处的电压是放大级的差分模式（DM）参考电位。

    SAMPLING NETWORK AND CLOCKING SCHEME FOR A SWITCHED-CAPACITOR INTEGRATOR
    6.
    发明申请
    SAMPLING NETWORK AND CLOCKING SCHEME FOR A SWITCHED-CAPACITOR INTEGRATOR 审中-公开
    开关电容器整流器的采样网络和时钟方案

    公开(公告)号：WO2016153813A1

    公开(公告)日：2016-09-29

    申请号：PCT/US2016/021917

    申请日：2016-03-11

    Applicant: QUALCOMM INCORPORATED

    Inventor： HUANG, Wenchang ,  SIVAKUMAR, Ramkumar

    IPC: H03M3/00

    CPC classification number: G11C27/026 ,  H03H19/004 ,  H03M3/342

    Abstract: Certain aspects of the present disclosure generally relate to a sampling network of a switched-capacitor integrator and a clocking scheme associated therewith, which may be used in an analog-to-digital converter (ADC), for example. The integrator generally includes five sets of switches which allow for a decreased switching frequency (e.g., halved) at an input stage of the integrator compared to conventional double sampling networks. As a result, the input impedance of the integrator may be increased (e.g., doubled), resulting in lower power consumption and reduced strain on driving circuitry.

    Abstract translation: 本公开的某些方面通常涉及开关电容积分器的采样网络和与其相关联的时钟方案，其可以例如在模数转换器（ADC）中使用。 积分器通常包括五组开关，其允许与常规双采样网络相比在积分器的输入级降低开关频率（例如，减半）。 结果，积分器的输入阻抗可以增加（例如，加倍），导致较低的功率消耗和减小的驱动电路的应变。

    AMPLIFIER WITH IMPROVED NOISE REDUCTION
    7.
    发明申请
    AMPLIFIER WITH IMPROVED NOISE REDUCTION 审中-公开
    具有改进噪声降噪功能的放大器

    公开(公告)号：WO2014209719A1

    公开(公告)日：2014-12-31

    申请号：PCT/US2014/042965

    申请日：2014-06-18

    Applicant: QUALCOMM INCORPORATED

    Inventor： HUANG, Wenchang ,  DHANASEKARAN, Vijayakumar

    IPC: H03F1/30 ,  H03F3/187 ,  H03F3/72 ,  H03F3/30 ,  H03G3/34

    CPC classification number: H03F1/305 ,  H03F3/187 ,  H03F3/3022 ,  H03F3/72 ,  H03F2200/03 ,  H03F2200/381 ,  H03F2200/411 ,  H03F2200/453 ,  H03F2200/456 ,  H03F2203/45136 ,  H03F2203/7236 ,  H03G3/348

    Abstract: An amplifier with improved noise reduction is disclosed. In an exemplary embodiment, an apparatus (300) includes at least one capacitor (326) configured to receive an adjustable current and generate a corresponding ramp voltage (Vy) configured to control coupling between a main amplifier output and a secondary amplifier output. The apparatus (300) also includes at least one comparator (M1, M2) configured to adjust the adjustable current to generate the ramp voltage (Vy) with selected ramp-up or ramp-down voltage characteristics.

    Abstract translation: 公开了一种具有改进的降噪功能的放大器。 在一个示例性实施例中，装置（300）包括至少一个电容器（326），其被配置为接收可调电流并产生配置成控制主放大器输出和辅助放大器输出之间的耦合的对应斜坡电压（Vy）。 装置（300）还包括至少一个比较器（M1，M2），其配置成调节可调电流以产生具有选定的斜升或斜降电压特性的斜坡电压（Vy）。

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