公开(公告)号：WO2019091358A1

公开(公告)日：2019-05-16

申请号：PCT/CN2018/114041

申请日：2018-11-06

Applicant: 深圳锐越微技术有限公司

Inventor： 郭啸峰 ,  冯海刚 ,  戴思特 ,  张宁 ,  檀聿麟

IPC: H03M1/12

CPC classification number: H03M1/1245 ,  H03M1/468

Abstract: 本申请公开一种N位混合结构模数转换器及包括其的集成电路芯片，该模数转换器器包括前级采样电容阵列、后级电容阵列以及比较器组，前级采样电容阵列包括2N-1组并列排布的第一电容阵列单元，第一电容阵列单元包括两组并联电容串，并联电容串的输入端分别与差分模拟信号及第一预设参考信号切换连接，输出端分别与比较器组的输入端连接，后级电容阵列的输入端分别与比较器组的输出及差分模拟信号切换连接，后级电容阵列的输出端作为模数转换器的输出；该N位混合结构模数转换器的纯电容阵列对于模拟差分信号友好；模拟差分信号的两路差分输入可共用同一比较器单元。

公开(公告)号：WO2017052892A1

公开(公告)日：2017-03-30

申请号：PCT/US2016/048143

申请日：2016-08-23

Applicant: QUALCOMM INCORPORATED

Inventor： HU, Weibo ,  HUANG, Wenchang

IPC: G11C27/02

CPC classification number: H03M1/1245 ,  G11C27/024 ,  G11C27/026

Abstract: Devices and methods for analog to digital conversion are provided. The device can have a supply voltage coupled to a bootstrap circuit operable to provide a boosted voltage during a first period defined by a sample phase (Ps) signal and a hold phase (Ph) signal. The device can also have a sampling circuit having an input node and operable to sample an input signal supplied to the input node. The device can also have a switching circuit having a first switch and a second switch. The switching circuit can be coupled to the bootstrap circuit and to the sampling circuit. The switching circuit can be configured to isolate the input node from shorting currents to the supply voltage for a portion of the first period.

Abstract translation: 提供了模数转换的设备和方法。 该装置可以具有耦合到自举电路的电源电压，该自举电路可操作以在由采样相位（Ps）信号和保持相位（Ph）信号定义的第一周期期间提供升压电压。 该装置还可以具有具有输入节点的采样电路，并且可操作以对提供给输入节点的输入信号进行采样。 该装置还可以具有具有第一开关和第二开关的开关电路。 开关电路可以耦合到自举电路和采样电路。 开关电路可以被配置为在第一周期的一部分期间将输入节点与短路电流隔离到电源电压。

公开(公告)号：WO2016179471A1

公开(公告)日：2016-11-10

申请号：PCT/US2016/031149

申请日：2016-05-06

Applicant: TEXAS INSTRUMENTS INCORPORATED ,  TEXAS INSTRUMENTS JAPAN LIMITED

Inventor： PATUKURI, Raja, Reddy ,  VENKATARAMAN, Jagannathan ,  THIRUGNANAM, Prabu, Sankar

IPC: H03M1/12

CPC classification number: H03M1/164 ,  G01S7/4863 ,  G01S17/89 ,  H03M1/1245 ,  H03M1/1295

Abstract: In described examples, a circuit (300) includes a first analog to digital converter (ADC) (306) that generates a coarse output in response to a first input (302) and a second input (304). The first ADC (306) generates the coarse output in a differential phase. A pipeline ADC (320) generates a differential signal (330) in response to the coarse output, the first input (302) and the second input (304). The pipeline ADC (320) generates the differential signal (330) in a common-mode phase. The first ADC (306) generates a common mode signal (310) in the common-mode phase.

Abstract translation: 在所描述的示例中，电路（300）包括响应于第一输入（302）和第二输入（304）产生粗略输出的第一模数转换器（ADC）（306）。 第一个ADC（306）在差分相位产生粗略输出。 流水线ADC（320）响应于粗略输出，第一输入（302）和第二输入（304）产生差分信号（330）。 流水线ADC（320）在共模相位产生差分信号（330）。 第一ADC（306）在共模相位中产生共模信号（310）。

公开(公告)号：WO2015131197A9

公开(公告)日：2016-08-25

申请号：PCT/US2015018343

申请日：2015-03-02

Applicant: TEXAS INSTRUMENTS INC ,  TEXAS INSTRUMENTS JAPAN

Inventor： HARRINGTON CORMAC ,  MOUSHEGIAN KEN ,  ALLEMAN ANDREW

IPC: H03M1/10 ,  H03M1/12

CPC classification number: H03M1/1004 ,  H03M1/1033 ,  H03M1/109 ,  H03M1/1095 ,  H03M1/12 ,  H03M1/1245

Abstract: In described examples, a method of testing linearity of an ADC includes receiving (1310) a trigger signal indicating an ADC input voltage step adjustment, and reading (1311) an ADC output sample upon receiving the trigger signal. The ADC output sample has a value range of N integer values that correspond to N discrete ADC output codes. Also, the method includes computing (1312) a histogram of code occurrences for M consecutive ADC output codes. The histogram includes M number of bins corresponding to the M consecutive ADC output codes, where M is less than N. Further, the method includes updating a DNL value and an INL value according to the histogram at an interval of K number of ADC output sample readings, and shifting (1330) the histogram by one ADC output code after updating the DNL and the INL values.

Abstract translation: 在所描述的示例中，测试ADC的线性度的方法包括接收（1310）指示ADC输入电压阶跃调整的触发信号，以及在接收到触发信号时读取（1311）ADC输出采样。 ADC输出采样的N个整数值的值范围对应于N个离散ADC输出代码。 此外，该方法包括计算（1312）M个连续ADC输出代码的码出现直方图。 该直方图包括对应于M个连续ADC输出代码的M个数目的M个数，其中M小于N.此外，该方法包括根据直方图以K个ADC输出样本的间隔更新DNL值和INL值 读数，并在更新DNL和INL值之后，通过一个ADC输出代码将直方图（1330）移位（1330）。

公开(公告)号：WO2016090353A2

公开(公告)日：2016-06-09

申请号：PCT/US2015/064191

申请日：2015-12-07

Applicant: TEXAS INSTRUMENTS INCORPORATED ,  TEXAS INSTRUMENTS JAPAN LIMITED

Inventor： SAKURAI, Satoshi

CPC classification number: H03M1/1245 ,  G11C27/02 ,  G11C27/026 ,  H03K19/01812 ,  H03M1/12

Abstract: In described examples of systems and methods for load current compensation for analog input buffers, an input buffer (300) may include: a first transistor (Q 1 ) having a collector terminal coupled to a power supply node and a base terminal coupled to a first input node (vinp); a second transistor (Q 2 ) having a collector terminal coupled to an emitter terminal of the first transistor (Q 1 ); a third transistor (Q 3 ) having an emitter terminal coupled to an emitter terminal of the second transistor (Q 2 ) and to a ground node, a collector terminal coupled to a current source (I bias ), and a base terminal coupled to the collector terminal and to a base terminal of the second transistor (Q 2 ); and a capacitor (C 1 ) coupled to the base terminals of the second and third transistors (Q 2 and Q 3 ) and to a second input node (v inn ), wherein the first and second input nodes (v inp and V inn ) are differential inputs.

Abstract translation: 在所描述的用于模拟输入缓冲器的负载电流补偿的系统和方法的示例中，输入缓冲器（300）可以包括：第一晶体管（Q 1），其具有集电极 耦合到电源节点的基极和耦合到第一输入节点（vinp）的基极; 具有耦合到第一晶体管（Q 1）的发射极端子的集电极端子的第二晶体管（Q 2） 具有耦合到第二晶体管（Q 2）的发射极端子的发射极端子和接地节点的第三晶体管（Q 3），集电极端子耦合到第二晶体管 电流源（I bias），以及耦合到集电极端子和第二晶体管（Q 2）的基极端子的基极端子; 和耦合到第二和第三晶体管（Q 2和Q 3）的基极端的电容器（C 1）以及耦合到第二和第三晶体管（Q 2和Q 3）的基极端的电容器 输入节点（v inn），其中第一和第二输入节点（v inp和v inn）是差分输入。

公开(公告)号：WO2016015224A1

公开(公告)日：2016-02-04

申请号：PCT/CN2014/083239

申请日：2014-07-29

Applicant: 华为技术有限公司

Inventor： 朱胡飞

IPC: H04L27/26

CPC classification number: H03D7/165 ,  H03M1/1245 ,  H04B1/005 ,  H04B1/30 ,  H04L27/26

Abstract: 本发明提供接收机和信号处理方法。接收机包括：第一混频器，用方波信号对接收信号混频得到第一混频信号；第一低通滤波器，对第一混频信号滤波得到第一滤波信号；第一模数转换器，对第一滤波信号模数模数转换得到第一釆样信号；信号处理单元，根据第一釆样信号估计发射端传输的信息符号，其中方波信号根据接收信号的载频的估计值产生。本发明实施例的接收机具有更好的灵活性。

公开(公告)号：WO2015120315A1

公开(公告)日：2015-08-13

申请号：PCT/US2015/014890

申请日：2015-02-06

Applicant: MASSACHUSETTS INSTITUTE OF TECHNOLOGY

Inventor： LEE, Sunghyuk ,  LEE, Hae-Seung ,  CHANDRAKASAN, Anantha

IPC: H03M1/38

CPC classification number: H03M1/0609 ,  H03M1/002 ,  H03M1/0836 ,  H03M1/121 ,  H03M1/1215 ,  H03M1/123 ,  H03M1/1245 ,  H03M1/181 ,  H03M1/46

Abstract: A time-interleaved (TI) analog-to-digital converter (ADC) architecture employs a low resolution coarse ADC channel that samples an input analog signal at a Nyquist rate and facilitates background calibration of timing-skew error without interrupting normal operation to sample/convert the input signal. The coarse ADC channel provides a timing reference for multiple higher resolution TI ADC channels that respectively sample the input signal at a lower sampling rate. The coarse ADC digital output is compared to respective TI ADC digital outputs to variably adjust in time corresponding sampling clocks of the TI ADC channels so as to substantially align them with the sampling clock of the coarse ADC channel, thus reducing timing-skew error. In one example, the coarse ADC output provides the most significant bits (MSBs) of the respective TI ADC digital outputs to further improve conversion speed and reduce power consumption in these channels.

Abstract translation: 时间交织（TI）模数转换器（ADC）架构采用低分辨率粗ADC通道，以奈奎斯特速率对输入模拟信号进行采样，便于定时偏移误差的背景校准，而不会中断对采样/ 转换输入信号。 粗ADC通道为多个更高分辨率的TI ADC通道提供了时序参考，分别以较低的采样率采样输入信号。 将粗ADC数字输出与相应的TI ADC数字输出进行比较，可随时调整TI ADC通道的相应采样时钟，使其与粗ADC通道的采样时钟基本对齐，从而减少定时偏移误差。 在一个示例中，粗ADC输出提供相应TI ADC数字输出的最高有效位（MSB），以进一步提高转换速度并降低这些通道的功耗。

公开(公告)号：WO2015051096A1

公开(公告)日：2015-04-09

申请号：PCT/US2014/058788

申请日：2014-10-02

Applicant: MICROCHIP TECHNOLOGY INCORPORATED

Inventor： GAO, Xiang

IPC: H03M1/12

CPC classification number: G01R15/002 ,  G01R1/30 ,  G01R27/2605 ,  H03M1/1245

Abstract: Relative capacitance of a plurality of capacitive sensors may be monitored by using only one ADC conversion. A plurality of capacitive sensors individually charges a sample and hold capacitor. After all of the plurality of capacitive sensors have charged the sample and hold capacitor, a digital conversion of the resulting analog on the sample and hold capacitor is made and stored in a memory. This stored digital collective voltage is compared to a previously stored one and if different then a proximity/touch event may have occurred. Therefore, an entire panel of capacitive sensors may be quickly monitored for a change in the "group" capacitance thereof, or portions of the capacitive sensors may be monitored for a change in the "subgroup" capacitance thereof. By knowing which subgroup of capacitive sensors has changed its collective capacitive value, a more focused and selective capacitive sensor measurement can be made that uses less power.

Abstract translation: 可以通过仅使用一个ADC转换来监视多个电容传感器的相对电容。 多个电容式传感器分别对采样和保持电容器充电。 在所有多个电容式传感器已经对采样和保持电容器充电之后，将所得到的模拟量在采样和保持电容器上进行数字转换并存储在存储器中。 将该存储的数字集合电压与先前存储的数字集合电压进行比较，如果不同，则可能发生接近/触摸事件。 因此，可以快速监测整个电容传感器面板的“组”电容的变化，或者可以监视电容传感器的部分，以使其“子组”电容发生变化。 通过知道哪个子组的电容式传感器已经改变了它的集体电容值，可以使用较少功率的更集中和选择性的电容传感器测量。

公开(公告)号：WO2015041880A1

公开(公告)日：2015-03-26

申请号：PCT/US2014/054519

申请日：2014-09-08

Applicant: QUALCOMM INCORPORATED

Inventor： BUTTERFIELD, Daniel Keyes ,  VERMA, Sumit ,  DUNWORTH, Jeremy Darren ,  SUN, Bo

IPC: H04B1/04 ,  H03M3/00

CPC classification number: H03M1/1245 ,  H03M3/344 ,  H03M3/504 ,  H04B1/0007 ,  H04B1/04 ,  H04B1/38

Abstract: A transmitter includes a delta-sigma modulator (100) characterized by a noise transfer function having a multitude of zeroes positioned substantially near a frequency band of a receive signal. The transmitter further includes, in part, a multi-phase digital-to-analog converter, DAC (200), converting an output signal of the delta- sigma modulator to an analog signal. The DAC is characterized by a transfer function that passes the desired signal to its output and attenuates a multitude of images of the sampling clock signal. The transmitter transmits at a frequency defined by an odd multiple of a fraction of the sampling clock signal frequency. The DAC includes a number of stages each pair of which is associated with one of the images being attenuated. The delta-sigma modulator includes a multitude of stages each associated with a different one of the zeroes. Each stage of said delta-sigma modulator optionally receives three tap coefficients.

Abstract translation: 发射机包括Δ-Σ调制器（100），其特征在于噪声传递函数具有基本上接近接收信号的频带的多个零点。 发射机还部分地包括将Δ-Σ调制器的输出信号转换为模拟信号的多相数模转换器DAC（200）。 DAC的特征在于将所需信号传递到其输出并衰减采样时钟信号的大量图像的传递函数。 发射机以由采样时钟信号频率的一部分的奇数倍定义的频率发射。 DAC包括多个阶段，每个阶段与被衰减的图像中的一个相关联。 Δ-Σ调制器包括多个级，其各自与不同的一个零相关联。 所述Δ-Σ调制器的每个级可任选地接收三个抽头系数。

公开(公告)号：WO2014189897A1

公开(公告)日：2014-11-27

申请号：PCT/US2014/038742

申请日：2014-05-20

Applicant: ANALOG DEVICES, INC.

Inventor： WEBER, Theophane ,  MCCORMICK, Martin ,  MENG, Qingdong

IPC: H03F1/32

CPC classification number: H04B1/0475 ,  H03F1/3247 ,  H03M1/002 ,  H03M1/1245 ,  H04L25/03019

Abstract: An approach to linearization relaxes the requirements on the digitization of the analog output signal while maintaining the benefits of a high sampling rate of the output signal. The digitization approach extracts sufficient information to characterize the output signal over a wide bandwidth without necessarily determining sufficient information to fully represent the output signal, for example, without sampling the output signal at the Nyquist sampling rate with a sufficient precision to accurately represent the signal.

Abstract translation: 线性化的方法放松了对模拟输出信号数字化的要求，同时保持了输出信号的高采样率的好处。 数字化方法提取足够的信息以在宽带宽上表征输出信号，而不必确定足够的信息以完全表示输出信号，例如，不以具有足够精度的奈奎斯特采样率对输出信号进行采样以精确地表示信号。