CIRCUITS FOR SEMICONDUCTOR DEVICE LEAKAGE CANCELLATION
    1.
    发明申请
    CIRCUITS FOR SEMICONDUCTOR DEVICE LEAKAGE CANCELLATION 审中-公开
    用于半导体器件泄漏电路的电路

    公开(公告)号:WO2014209662A1

    公开(公告)日:2014-12-31

    申请号:PCT/US2014/042602

    申请日:2014-06-17

    Abstract: One feature pertains to a circuit comprising a semiconductor leakage source device and a semiconductor leakage cancellation device that are both coupled to a signal line. The leakage source device generates a leakage current on the signal line, and the leakage cancellation device generates a leakage cancellation current on the signal line. The leakage cancellation device is sized and shaped in relation to the leakage source device such that the leakage cancellation current effectively cancels the leakage current on the signal line. Moreover, the leakage cancellation current cancels the leakage current on the signal line despite variations in at least one of process, temperature, and/or signal line voltages. In one example, the signal line is a virtual ground node of a capacitive feedback amplifier and the leakage source device is a switch between the virtual ground node and a first terminal of a feedback capacitor of the amplifier.

    Abstract translation: 一个特征涉及包括耦合到信号线的半导体泄漏源装置和半导体泄漏消除装置的电路。 泄漏源装置在信号线上产生泄漏电流,泄漏消除装置在信号线上产生泄漏消除电流。 泄漏消除装置的尺寸和形状相对于泄漏源装置成形,使得泄漏抵消电流有效地消除信号线上的泄漏电流。 此外,尽管在工艺,温度和/或信号线电压中的至少一个有变化,但是泄漏抵消电流消除了信号线上的漏电流。 在一个示例中,信号线是电容性反馈放大器的虚拟接地节点,并且泄漏源装置是虚拟接地节点与放大器的反馈电容器的第一端子之间的开关。

    AREA EFFICIENT LEVEL TRANSLATING TRIGGER CIRCUIT FOR ELECTROSTATIC DISCHARGE EVENTS

    公开(公告)号:WO2023086173A1

    公开(公告)日:2023-05-19

    申请号:PCT/US2022/045921

    申请日:2022-10-06

    Abstract: A trigger circuit includes a first capacitor and a second capacitor connected in series, a control device and an output of the trigger circuit. The first capacitor is connected to a first voltage rail and to a common node. The second capacitor is connected to a second voltage rail and to the common node. The control device has a first terminal that is coupled to the common node and a control terminal to receive a control signal. The control signal may be decoupled from transients on the first voltage rail and the second voltage rail. The output of the trigger circuit is coupled to the common node.

    SYSTEM AND METHOD FOR SUPPLYING POWER ON DEMAND TO A DYNAMIC LOAD
    4.
    发明申请
    SYSTEM AND METHOD FOR SUPPLYING POWER ON DEMAND TO A DYNAMIC LOAD 审中-公开
    用于向动态负载供电的系统和方法

    公开(公告)号:WO2010141896A2

    公开(公告)日:2010-12-09

    申请号:PCT/US2010/037510

    申请日:2010-06-04

    Abstract: An apparatus for supplying power to a load. The apparatus including a plurality of sources to provide charge, and a controller adapted to control a transfer of charge from the sources to the load at distinct times. The controller may control the transfer of charge based on variation of an ambient condition or a manufacturing process. The controller may control the transfer of charge to generate a defined voltage across the load. The apparatus may include a regulator adapted to regulate a voltage across the load. The regulator may regulate the voltage across the load in a defined timing relationship with the transfer of charge from the sources to the load.

    Abstract translation: 一种用于向负载供电的装置。 该装置包括用于提供电荷的多个源,以及控制器,其适于控制在不同时间从电荷到负载的电荷转移。 控制器可以基于环境条件或制造过程的变化来控制电荷的转移。 控制器可以控制电荷的转移以在负载两端产生限定的电压。 该装置可以包括适于调节负载两端的电压的调节器。 调节器可以在与源到负载的电荷转移的限定时序关系中调节负载两端的电压。

    SAMPLING NETWORK AND CLOCKING SCHEME FOR A SWITCHED-CAPACITOR INTEGRATOR
    6.
    发明申请
    SAMPLING NETWORK AND CLOCKING SCHEME FOR A SWITCHED-CAPACITOR INTEGRATOR 审中-公开
    开关电容器整流器的采样网络和时钟方案

    公开(公告)号:WO2016153813A1

    公开(公告)日:2016-09-29

    申请号:PCT/US2016/021917

    申请日:2016-03-11

    CPC classification number: G11C27/026 H03H19/004 H03M3/342

    Abstract: Certain aspects of the present disclosure generally relate to a sampling network of a switched-capacitor integrator and a clocking scheme associated therewith, which may be used in an analog-to-digital converter (ADC), for example. The integrator generally includes five sets of switches which allow for a decreased switching frequency (e.g., halved) at an input stage of the integrator compared to conventional double sampling networks. As a result, the input impedance of the integrator may be increased (e.g., doubled), resulting in lower power consumption and reduced strain on driving circuitry.

    Abstract translation: 本公开的某些方面通常涉及开关电容积分器的采样网络和与其相关联的时钟方案,其可以例如在模数转换器(ADC)中使用。 积分器通常包括五组开关,其允许与常规双采样网络相比在积分器的输入级降低开关频率(例如,减半)。 结果,积分器的输入阻抗可以增加(例如,加倍),导致较低的功率消耗和减小的驱动电路的应变。

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