公开(公告)号：WO2018144207A1

公开(公告)日：2018-08-09

申请号：PCT/US2018/013636

申请日：2018-01-12

Applicant: QUALCOMM INCORPORATED

Inventor： SONG, Yu ,  ZHU, Zhi ,  LI, Miao ,  SUN, Li ,  SONG, Deqiang ,  CHANG, Chia Heng

IPC: H04L7/00 ,  H03L7/081 ,  H04L7/033

Abstract: Systems and methods for adjusting a phase step size of a clock data recover (CDR) circuit are described according to aspects of the present disclosure. In certain aspects, a method for adjusting a phase step size of a CDR circuit includes sensing a frequency offset of the CDR circuit, and adjusting the phase step size of the CDR circuit based on the sensed frequency offset. The frequency offset may be sensed by sensing a signal level on an integration path of a loop filter of the CDR circuit. The phase step size of the CDR circuit may be adjusted by switching the CDR circuit between a first phase step size and a second phase step size using a modulator (e.g., a sigma-delta modulator).

公开(公告)号：WO2014066152A1

公开(公告)日：2014-05-01

申请号：PCT/US2013/065592

申请日：2013-10-18

Applicant: QUALCOMM INCORPORATED

Inventor： LI, Miao ,  ZHUANG, Jingcheng ,  HU, Yan ,  BAI, Xiaoliang ,  KANG, Jing

IPC: H03K19/00 ,  H03K19/0175

CPC classification number: H03K19/017554 ,  H03K19/0005

Abstract: An output driver for electrostatic discharge (ESD) protection includes a first pair of stacked metal oxide semiconductor field-effect transistor (MOS) devices coupled between a power terminal and a first differential output terminal. The output driver also includes a second pair of stacked MOS devices coupled between a second differential output terminal and a ground terminal.

Abstract translation: 用于静电放电（ESD）保护的输出驱动器包括耦合在电源端子和第一差分输出端子之间的第一对堆叠金属氧化物半导体场效应晶体管（MOS）器件。 输出驱动器还包括耦合在第二差分输出端子和接地端子之间的第二对堆叠MOS器件。

公开(公告)号：WO2016025070A1

公开(公告)日：2016-02-18

申请号：PCT/US2015/035781

申请日：2015-06-15

Applicant: QUALCOMM INCORPORATED

Inventor： LI, Miao ,  KONG, Xiaohua ,  REN, Dong

IPC: H03F1/02 ,  H03F3/45 ,  H03F3/50 ,  H04L25/02

CPC classification number: H03F3/505 ,  H03F1/0272 ,  H03F3/45183 ,  H03F3/4565 ,  H03F3/45708 ,  H03F2200/453 ,  H03F2200/78 ,  H03F2203/45292 ,  H03F2203/45416 ,  H03F2203/45418 ,  H03F2203/45424 ,  H03F2203/45594 ,  H03F2203/45604 ,  H03F2203/45664 ,  H03F2203/45702 ,  H04L25/0276

Abstract: Techniques for converting a signal from a small-signal format into a rail-to-rail format are described herein. In one embodiment, a receiver comprises a voltage-level shifter configured to shift a common-mode voltage of a differential signal to obtain a level-shifted differential signal, an amplifier configured to amplify the level-shifted differential signal into an amplified differential signal, and a driver stage configured to convert the amplified differential signal into a rail-to-rail signal. The receiver also comprises a common-mode feedback circuit configured to generate a feedback voltage that is proportional to an output common-mode voltage of the amplifier, and to generate a bias voltage for input to the amplifier based on a difference between the feedback voltage and a reference voltage, wherein the output common-mode voltage of the amplifier depends on the bias voltage.

Abstract translation: 这里描述了用于将信号从小信号格式转换为轨到轨格式的技术。 在一个实施例中，接收机包括：电压电平移位器，被配置为移位差分信号的共模电压以获得电平移位的差分信号;放大器，被配置为将电平移位的差分信号放大为放大的差分信号， 以及驱动器级，被配置为将放大的差分信号转换成轨到轨信号。 接收机还包括共模反馈电路，其被配置为产生与放大器的输出共模电压成比例的反馈电压，并且基于反馈电压和反馈电压之间的差产生用于输入到放大器的偏置电压 参考电压，其中放大器的输出共模电压取决于偏置电压。

公开(公告)号：WO2013049757A1

公开(公告)日：2013-04-04

申请号：PCT/US2012/058172

申请日：2012-09-30

Applicant: QUALCOMM INCORPORATED ,  ZHONG, Cheng ,  DANG, Vannam ,  LI, Miao ,  MAAROUF, Fares K. ,  SOWLATI, Tirdad

Inventor： ZHONG, Cheng ,  DANG, Vannam ,  LI, Miao ,  MAAROUF, Fares K. ,  SOWLATI, Tirdad

IPC: H04L25/02 ,  H03K19/0185

CPC classification number: H04L25/0274 ,  H04L25/0278

Abstract: A differential voltage mode driver for implementing symmetric single ended termination includes an output driver circuitry having a predefined termination impedance. The differential voltage mode driver also includes an output driver replica having independently controlled first and second portions. The first and second portions are independently controlled to establish a substantially equal on-resistance of the first and the second portions. The output driver replica controls the predefined termination impedance of the output driver circuitry.

Abstract translation: 用于实现对称单端终端的差分电压模式驱动器包括具有预定义的终端阻抗的输出驱动器电路。 差分电压模式驱动器还包括具有独立控制的第一和第二部分的输出驱动器副本。 独立地控制第一和第二部分以建立第一和第二部分的基本相等的导通电阻。 输出驱动器副本控制输出驱动器电路的预定终止阻抗。

公开(公告)号：WO2013016466A1

公开(公告)日：2013-01-31

申请号：PCT/US2012/048207

申请日：2012-07-25

Applicant: QUALCOMM INCORPORATED ,  LI, Miao ,  KONG, Xiaohua ,  DANG, Nam V. ,  ZHONG, Cheng

Inventor： LI, Miao ,  KONG, Xiaohua ,  DANG, Nam V. ,  ZHONG, Cheng

IPC: G09G5/00 ,  H04L1/00 ,  H04L1/20 ,  H04N5/00

CPC classification number: G01R31/3177 ,  G06F1/04 ,  G09G5/006 ,  G09G2350/00 ,  G09G2370/12

Abstract: System and method for testing a high speed data path without generating a high speed bit clock, includes selecting a first high speed data path from a plurality of data paths for testing. Coherent clock data patterns are driven on one or more of remaining data paths of the plurality of data paths, wherein the coherent clock data patterns are in coherence with a low speed base clock. The first high speed data path is sampled by the coherent clock data patterns to generate a sampled first high speed data path, which is then tested at a speed of the low speed base clock.

Abstract translation: 用于测试高速数据路径而不产生高速位时钟的系统和方法包括从多个数据路径中选择第一高速数据路径进行测试。 在多个数据路径中的一个或多个剩余数据路径上驱动相干时钟数据模式，其中相干时钟数据模式与低速基准时钟保持一致。 第一高速数据路径被相干时钟数据模式采样，以产生采样的第一高速数据路径，然后以低速基准时钟的速度进行测试。

公开(公告)号：WO2021113113A1

公开(公告)日：2021-06-10

申请号：PCT/US2020/061903

申请日：2020-11-24

Applicant: QUALCOMM INCORPORATED

Inventor： LI, Miao ,  SONG, Yu ,  XU, Jie

IPC: H03F1/56 ,  H03F3/21 ,  H03F3/72 ,  H03K19/00 ,  H03K19/0185 ,  H03M9/00 ,  H03F3/45 ,  H04L25/02

Abstract: A data transmitter includes: a plurality of parallel driver slices, a first slice of the plurality of parallel driver slices having a first signal generator circuit with a first transistor coupled to a data signal and in series with a second transistor coupled to a first bias signal; and a first bias circuit including a third transistor and a fourth transistor in series with a first current source, the first bias circuit further including a first operational amplifier (op amp) having a first input coupled to a first reference voltage and a second input coupled between the fourth transistor and the first current source, an output of the first op amp configured to provide the first bias signal to the second transistor and to the third transistor.

公开(公告)号：WO2021113112A1

公开(公告)日：2021-06-10

申请号：PCT/US2020/061900

申请日：2020-11-24

Applicant: QUALCOMM INCORPORATED

Inventor： LI, Miao ,  SUN, Li ,  LIU, Hao

IPC: H03F1/30 ,  H03F3/45 ,  H03G3/30 ,  H04L25/03

Abstract: A bias structure includes a reference voltage node connected to gate structures of a first NMOS transistor and a second NMOS transistor, a bias voltage node comprising a bias voltage, and a first op amp having a first input connected to the reference voltage, a second input connected to a drain of the first NMOS transistor, and an output connected to gate structures of a first PMOS transistor and a second PMOS transistor. The bias structure further includes a second op amp having a first input connected to the reference voltage, a second input connected to a drain of the second NMOS transistor, and an output connected to a gate structure of a third NMOS transistor and the bias voltage node. The first NMOS transistor matches a transistor of a differential pair of an integrated circuit device.

公开(公告)号：WO2013071275A2

公开(公告)日：2013-05-16

申请号：PCT/US2012/064732

申请日：2012-11-12

Applicant: QUALCOMM INCORPORATED

Inventor： LI, Miao ,  KONG, Xiaohua ,  DANG, Nam V.

IPC: H03F3/45

CPC classification number: H03F1/223 ,  H03F3/195 ,  H03F3/245 ,  H03F3/45085 ,  H03F3/45659 ,  H03F2203/45418 ,  H03F2203/45696 ,  H03F2203/45702 ,  H03F2203/45726

Abstract: A multi-terminal output with a common mode connection includes an output having a first terminal and a second terminal and having a common mode connection between the first terminal and the second terminal. A bulk connection of a transistor is coupled to the common mode connection. A first set of control signals and a second set of control signals are generated. Each of the first set of control signals has a first rail voltage level associated with a first power domain. The second set of control signals is generated from the first set of control signals. Each of the second set of control signals has a second rail voltage level that is associated with a second power domain. The second power domain is associated with a common mode voltage of outputs of an output driver.

Abstract translation: 具有共模连接的多端子输出包括具有第一端子和第二端子的输出端，并且在第一端子和第二端子之间具有共模连接。 晶体管的体连接耦合到共模连接。 产生第一组控制信号和第二组控制信号。 第一组控制信号中的每一个具有与第一功率域相关联的第一导轨电压电平。 第二组控制信号是从第一组控制信号产生的。 第二组控制信号中的每一个具有与第二功率域相关联的第二轨电压电平。 第二功率域与输出驱动器的输出的共模电压相关联。

公开(公告)号：WO2017053119A1

公开(公告)日：2017-03-30

申请号：PCT/US2016/051356

申请日：2016-09-12

Applicant: QUALCOMM INCORPORATED

Inventor： SUN, Li ,  KONG, Xiaohua ,  ZHU, Zhi ,  LI, Miao ,  REN, Dong

IPC: H04L25/03 ,  H04L25/02

CPC classification number: H04L27/01 ,  H04L25/0272 ,  H04L25/0292 ,  H04L25/03006 ,  H04L25/03146 ,  H04L25/03878

Abstract: In one embodiment, a receiver comprises a latch configured to receive a data signal and to latch symbols of the received data signal, and a decision feedback equalizer. The decision feedback equalizer comprises a first feedback capacitor having first and second terminals, the first terminal being coupled to a first internal node of the latch. The decision feedback equalizer also comprises a first plurality of switches configured to alternatively couple the second terminal of the first feedback capacitor to a first feedback signal and a ground, the first feedback signal having a first voltage that is a function of a bit decision corresponding to a first previous symbol in the data signal preceding a current symbol in the data signal.

Abstract translation: 在一个实施例中，接收机包括被配置为接收数据信号并锁存接收到的数据信号的符号的锁存器和判决反馈均衡器。 所述判决反馈均衡器包括具有第一和第二端子的第一反馈电容器，所述第一端子耦合到所述锁存器的第一内部节点。 判决反馈均衡器还包括配置成将第一反馈电容器的第二端子交替地耦合到第一反馈信号和接地的第一多个开关，第一反馈信号具有第一电压，其是对应于 在数据信号中的当前符号之前的数据信号中的第一先前符号。

公开(公告)号：WO2016114882A1

公开(公告)日：2016-07-21

申请号：PCT/US2015/065358

申请日：2015-12-11

Applicant: QUALCOMM INCORPORATED

Inventor： LI, Miao ,  SUN, Li ,  ZHU, Zhi

IPC: H03K19/003 ,  H03F3/45 ,  H03K19/0185

CPC classification number: H03F1/30 ,  H03F3/45076 ,  H03F3/45183 ,  H03F3/45197 ,  H03F3/4565 ,  H03F3/45766 ,  H03F2200/447 ,  H03F2200/543 ,  H03F2203/45048 ,  H03F2203/45101 ,  H03F2203/45116 ,  H03F2203/45244 ,  H03F2203/45456 ,  H03G1/0029 ,  H03G3/3036 ,  H03K19/00384 ,  H03K19/018528

Abstract: An apparatus is provided. The apparatus includes a calibration circuit (200) configured to generate a reference signal (VREF) and at least one differential circuit each being configured to operate at a calibrated transconductance over process or condition variations based on the reference signal. The calibration circuit (200) may be configured to generate the reference signal (VREF) independent of the at least one differential circuit. A method for operating at least one differential circuit is provided. The method includes generating a reference signal (VREF) and operating the at least one differential circuit at a calibrated transconductance or gain over process or condition variations based on the reference signal. The reference signal (VREF) may be generated independently of the at least one differential circuit.

Abstract translation: 提供了一种装置。 该装置包括被配置为产生参考信号（VREF）的校准电路（200）以及至少一个差分电路，每个差分电路被配置为基于参考信号在校准的跨导处超过过程或条件变化进行操作。 校准电路（200）可以被配置为生成独立于至少一个差分电路的参考信号（VREF）。 提供了一种用于操作至少一个差分电路的方法。 该方法包括产生参考信号（VREF）并且以校准的跨导或基于参考信号的过程或条件变化获得的增益来操作至少一个差分电路。 可以独立于至少一个差分电路来产生参考信号（VREF）。