公开(公告)号：WO2021113113A1

公开(公告)日：2021-06-10

申请号：PCT/US2020/061903

申请日：2020-11-24

Applicant: QUALCOMM INCORPORATED

Inventor： LI, Miao ,  SONG, Yu ,  XU, Jie

IPC: H03F1/56 ,  H03F3/21 ,  H03F3/72 ,  H03K19/00 ,  H03K19/0185 ,  H03M9/00 ,  H03F3/45 ,  H04L25/02

Abstract: A data transmitter includes: a plurality of parallel driver slices, a first slice of the plurality of parallel driver slices having a first signal generator circuit with a first transistor coupled to a data signal and in series with a second transistor coupled to a first bias signal; and a first bias circuit including a third transistor and a fourth transistor in series with a first current source, the first bias circuit further including a first operational amplifier (op amp) having a first input coupled to a first reference voltage and a second input coupled between the fourth transistor and the first current source, an output of the first op amp configured to provide the first bias signal to the second transistor and to the third transistor.

公开(公告)号：WO2014150625A1

公开(公告)日：2014-09-25

申请号：PCT/US2014/023829

申请日：2014-03-12

Applicant: QUALCOMM INCORPORATED

Inventor： SONG, Yu ,  CHEN, Nan

IPC: H03L7/087 ,  H03L7/089 ,  H03L7/093

CPC classification number: H03L7/0802 ,  H03L7/087 ,  H03L7/0891 ,  H03L7/0893 ,  H03L7/093

Abstract: Techniques for reducing noise and power consumption in a loop filter for a phase-locked loop (PLL) are described herein. In one embodiment, a loop filter for a PLL comprises a first proportional capacitor, a second proportional capacitor, an active device, and a plurality of switches. The plurality of switches are configured to alternately couple the first proportional capacitor and the second proportional capacitor to a first charge pump, to alternately couple noise from the active device to the first proportional capacitor and the second proportional capacitor, and to alternately couple the first proportional capacitor and the second proportional capacitor into a feedback circuit, wherein the feedback circuit produces an output voltage of the loop filter.

Abstract translation: 本文描述了用于降低锁相环（PLL）的环路滤波器中的噪声和功耗的技术。 在一个实施例中，用于PLL的环路滤波器包括第一比例电容器，第二比例电容器，有源器件和多个开关。 多个开关被配置为将第一比例电容器和第二比例电容器交替地耦合到第一电荷泵，以将来自有源器件的噪声交替耦合到第一比例电容器和第二比例电容器，并且交替地耦合第一比例电容器 电容器和第二比例电容器组成反馈电路，其中反馈电路产生环路滤波器的输出电压。

公开(公告)号：WO2014110371A1

公开(公告)日：2014-07-17

申请号：PCT/US2014/011046

申请日：2014-01-10

Applicant: QUALCOMM INCORPORATED

Inventor： DIFFENDERFER, Jan ,  SONG, Yu

IPC: H03K3/3565 ,  H03K19/0185

CPC classification number: G05F1/46 ,  H03K3/3565 ,  H03K19/018521

Abstract: A single-ended comparator is disclosed herein. The comparator may be implemented with low-voltage semiconductor devices that are capable of operating with high-voltage signals at an input. The single-ended comparator may be integrated in a larger circuit to receive and detect information provided on the input at voltage levels higher than the levels supported by the rest of the circuit, and transfer the information in the received signal for use by the rest of the circuit.

Abstract translation: 本文公开了单端比较器。 比较器可以用能够在输入端用高电压信号进行操作的低压半导体器件来实现。 单端比较器可以集成在较大的电路中以接收和检测在电路电平上提供的信号，该电平高于电路其余部分所支持的电平，并传送接收信号中的信息以供其余部分使用 电路。

公开(公告)号：WO2016160235A1

公开(公告)日：2016-10-06

申请号：PCT/US2016/020270

申请日：2016-03-01

Applicant: QUALCOMM INCORPORATED

Inventor： SONG, Yu ,  DAI, Liang

IPC: H03F1/30 ,  H03F1/32 ,  H03F3/26 ,  H03F1/02

CPC classification number: H03K17/165 ,  H03F1/0233 ,  H03F1/307 ,  H03F1/3217 ,  H03F3/26

Abstract: A push-pull driver is provided with a differential amplifier that amplifies a difference between an input voltage and an output voltage to drive a bias node coupled to a diode-connected bias transistor. The push-pull driver is configured to control the drain-to-source voltage for a source-follower output transistor having its gate tied to a gate for the diode-connected bias transistor to be proportional to the drain-to-source voltage for the diode-connected bias transistor. This proportionality prevents excessive static current variation that would otherwise be present in the source-follower output transistor.

Abstract translation: 推挽驱动器设置有差分放大器，其放大输入电压和输出电压之间的差以驱动耦合到二极管连接的偏置晶体管的偏置节点。 推挽驱动器被配置为控制源极跟随器输出晶体管的漏极 - 源极电压，其栅极连接到二极管连接的偏置晶体管的栅极与源极 - 源极电压成比例 二极管连接的偏置晶体管。 这种比例性可以防止在源极跟随器输出晶体管中存在的过大的静态电流变化。

公开(公告)号：WO2018144207A1

公开(公告)日：2018-08-09

申请号：PCT/US2018/013636

申请日：2018-01-12

Applicant: QUALCOMM INCORPORATED

Inventor： SONG, Yu ,  ZHU, Zhi ,  LI, Miao ,  SUN, Li ,  SONG, Deqiang ,  CHANG, Chia Heng

IPC: H04L7/00 ,  H03L7/081 ,  H04L7/033

Abstract: Systems and methods for adjusting a phase step size of a clock data recover (CDR) circuit are described according to aspects of the present disclosure. In certain aspects, a method for adjusting a phase step size of a CDR circuit includes sensing a frequency offset of the CDR circuit, and adjusting the phase step size of the CDR circuit based on the sensed frequency offset. The frequency offset may be sensed by sensing a signal level on an integration path of a loop filter of the CDR circuit. The phase step size of the CDR circuit may be adjusted by switching the CDR circuit between a first phase step size and a second phase step size using a modulator (e.g., a sigma-delta modulator).

公开(公告)号：WO2015167680A1

公开(公告)日：2015-11-05

申请号：PCT/US2015/020997

申请日：2015-03-17

Applicant: QUALCOMM INCORPORATED

Inventor： SONG, Yu ,  DIFFENDERFER, Jan Christian ,  CHEN, Nan ,  WEST, David Ian ,  VIANI, Paul Lawrence

IPC: H04L7/033 ,  H03L7/08

CPC classification number: H04L7/0016 ,  H03L7/0807 ,  H03L7/091 ,  H04L7/0083 ,  H04L7/0338

Abstract: Systems and methods for recovering clock and data from a data input signal are disclosed that sample a plurality of clock phase signals with the data input signal to determine a timing relationship between the data input signal and the clock phase signals and use the determined to timing relationship to select one of the clock phase signals to use for sampling the data input signal to produce recovered data. The CDR can include a glitch suppression module to suppress glitches on the clock output signal that could be caused by large instantaneous jitter on the data input signal. A clock and data recovery circuit (CDR) using these methods can quickly lock to a new data input signal and can reliably receive data when there is large instantaneous timing jitter on the data input signal.

Abstract translation: 公开了用于从数据输入信号恢复时钟和数据的系统和方法，用数据输入信号对多个时钟相位信号进行采样，以确定数据输入信号和时钟相位信号之间的定时关系，并使用确定的定时关系 选择一个时钟相位信号用于采样数据输入信号以产生恢复的数据。 CDR可以包括毛刺抑制模块，以抑制可能由数据输入信号上的大的瞬时抖动引起的时钟输出信号的毛刺。 使用这些方法的时钟和数据恢复电路（CDR）可以快速锁定到新的数据输入信号，并且可以在数据输入信号上存在大的瞬时定时抖动时可靠地接收数据。