公开(公告)号：WO2016040034A1

公开(公告)日：2016-03-17

申请号：PCT/US2015/047727

申请日：2015-08-31

Applicant: QUALCOMM INCORPORATED

Inventor： PASCARELLA, Randall, John ,  GANASAN, Jaya, Prakash Subramaniam ,  TRUONG, Thuong, Quang ,  RAJAMANI, Gurushankar ,  MCDONALD, Joseph, Gerald ,  SPEIER, Thomas, Philip

IPC: G06F13/40 ,  G06F13/16

CPC classification number: G06F13/4013 ,  G06F13/1621 ,  G06F13/4027 ,  G06F13/4059 ,  G06F13/4221

Abstract: Bridging strongly ordered write transactions to devices in weakly ordered domains, and related apparatuses, methods, and computer-readable media are disclosed. In one aspect, a host bridge device is configured to receive strongly ordered write transactions from one or more strongly ordered producer devices. The host bridge device issues the strongly ordered write transactions to one or more consumer devices within a weakly ordered domain. The host bridge device detects a first write transaction that is not accepted by a first consumer device of the one or more consumer devices. For each of one or more write transactions issued subsequent to the first write transaction and accepted by a respective consumer device, the host bridge device sends a cancellation message to the respective consumer device. The host bridge device replays the first write transaction and the one or more write transactions that were issued subsequent to the first write transaction.

Abstract translation: 公布了对弱排序域中的设备进行强有序的写入事务，并且公开了相关设备，方法和计算机可读介质。 在一个方面，主桥设备被配置为从一个或多个强排序的生成器设备接收强有序的写事务。 主桥设备向弱排序域中的一个或多个消费者设备发出强有序的写事务。 主桥设备检测不被一个或多个消费者设备的第一消费者设备接受的第一写事务。 对于在第一写入事务之后发出并由相应的消费者设备接受的一个或多个写入事务中的每一个，主桥设备向相应的消费者设备发送取消消息。 主桥设备重播第一个写入事务以及在第一次写入事务之后发出的一个或多个写入事务。

公开(公告)号：WO2019055599A1

公开(公告)日：2019-03-21

申请号：PCT/US2018/050806

申请日：2018-09-13

Applicant: QUALCOMM INCORPORATED

Inventor： ROBINSON, Eric, Francis ,  SPEIER, Thomas, Philip ,  MCDONALD, Joseph, Gerald ,  DRAPALA, Garrett, Michael ,  MAGILL, Kevin, Neal

IPC: G06F12/0831

CPC classification number: G06F12/0815 ,  G06F12/0831 ,  G06F13/1668 ,  G06F13/4027 ,  G06F2212/1021 ,  G06F2212/62

Abstract: Converting a stale cache memory unique request to a read unique snoop response in a multiple (multi-) central processing unit (CPU) processor is disclosed. The multi-CPU processor includes a plurality of CPUs that each have access to either private or shared cache memories in a cache memory system. Multiple CPUs issuing unique requests to write data to a same coherence granule in a cache memory causes one unique request for a requested CPU to be serviced or "win" to allow that CPU to obtain the coherence granule in a unique state, while the other unsuccessful unique requests become stale. To avoid retried unique requests being reordered behind other pending, younger requests which would lead to lack of forward progress due to starvation or livelock, the snooped stale unique requests are converted to read unique snoop responses so that their request order can be maintained in the cache memory system.