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    MINIMUM FINGER LOW-POWER DEMODULATOR FOR WIRELESS COMMUNICATION
    1.
    发明申请
    MINIMUM FINGER LOW-POWER DEMODULATOR FOR WIRELESS COMMUNICATION 审中-公开
    用于无线通信的最小手指低功率解调器

    公开(公告)号：WO2009065014A1

    公开(公告)日：2009-05-22

    申请号：PCT/US2008/083596

    申请日：2008-11-14

    Applicant: QUALCOMM Incorporated ,  HOWARD, Michael, Alexander ,  NAMGOONG, June ,  PAN, Hanfang

    Inventor： HOWARD, Michael, Alexander ,  NAMGOONG, June ,  PAN, Hanfang

    IPC: H04B1/707

    CPC classification number: H04B1/7117

    Abstract: Techniques for assigning multipaths to finger processors to achieve the desired data performance and low power consumption are described. A search is initially performed to obtain a set of multipaths for a transmission from at least one base station. At least one multipath (e.g., the minimum number of multipaths) having a combined performance metric (e.g., a combined SNR) exceeding a threshold is identified. The at least one multipath is assigned to, and processed by, at least one finger processor to recover the transmission from the base station(s).

    Abstract translation: 描述了将多路径分配给指状处理器以实现期望的数据性能和低功耗的技术。 最初执行搜索以获得用于来自至少一个基站的传输的一组多路径。 识别具有超过阈值的组合性能度量（例如，组合SNR）的至少一个多路径（例如，最小数量的多路径）。 至少一个多路径被分配给至少一个手指处理器并由其处理，以恢复来自基站的传输。

    EFFICIENT MULTI-SYMBOL DEINTERLEAVER
    3.
    发明申请
    EFFICIENT MULTI-SYMBOL DEINTERLEAVER 审中-公开
    有效的多符号检测器

    公开(公告)号：WO2005086358A1

    公开(公告)日：2005-09-15

    申请号：PCT/US2005/006635

    申请日：2005-02-25

    Applicant: QUALCOMM INCORPORATED ,  PAN, Hanfang ,  KANG, Inyup ,  KRYSL, James

    Inventor： PAN, Hanfang ,  KANG, Inyup ,  KRYSL, James

    IPC: H03M13/27

    CPC classification number: H03M13/2764 ,  H03M13/2703

    Abstract: Embodiments disclosed herein address the need in the art for an efficient multi-symbol deinterleaver. In one aspect, a plurality of memory banks are deployed to receive and simultaneously store a plurality of values, such as soft decision values determined from a modulation constellation, in accordance with a storing pattern. In another aspect, the storing pattern comprises a plurality of cycles, a selected subset of the plurality of memory banks and an address offset for use in determining the address for storing into the respective memory banks indicated for each cycle. In yet another aspect, the stored values may be accessed in order with a sequentially increasing index, such as an address. Various other aspects are also presented. These aspects have the benefit of allowing multiple symbol values to be deinterleaved in an efficient manner, thus meeting computation time constraints, and conserving power.

    Abstract translation: 本文公开的实施例解决了本领域对于有效的多符号解交织器的需要。 在一个方面，多个存储体被部署以根据存储模式来接收并同时存储多个值，诸如从调制星座确定的软判决值。 在另一方面，存储模式包括多个周期，多个存储体的选定子集和用于确定用于存储到为每个周期指示的相应存储体中的地址的地址偏移。 在另一方面，可以按顺序增加的索引（诸如地址）按顺序访问所存储的值。 还提出了各种其他方面。 这些方面具有允许以有效的方式解码多个符号值的好处，从而满足计算时间限制并节省功率。

    EDRAM BASED ARCHITECTURE
    4.
    发明申请
    EDRAM BASED ARCHITECTURE 审中-公开
    基于EDRAM的体系结构

    公开(公告)号：WO2003025947A2

    公开(公告)日：2003-03-27

    申请号：PCT/US2002/030000

    申请日：2002-09-19

    Applicant: QUALCOMM INCORPORATED

    Inventor： ZHANG, Haitao ,  SIMMONDS, Stephen, M. ,  PAN, Hanfang

    IPC: G11C11/406

    CPC classification number: G11C11/40622 ,  G11C11/406

    Abstract: A memory refresh system and method. The inventive system includesa mechanism for selectively refreshing elements of a memory arrayin response to signals from a conventional memory management system. In the illustrative application, the memory is dynamic randomaccess memory and the inventive system is adapted to provide for selective refresh of those DRAM memory elements to which data hasbeen or will be stored. This allows for the use of advantageous DRAM memory elements while minimizing the power consumption thereof. Consequently, the utility of DRAM memory elements is extended to a variety of power sensitive applications including cellular telephony and mobile computing.

    Abstract translation:

    存储器刷新系统和方法。 本发明的系统包括用于响应于来自传统存储器管理系统的信号而选择性地刷新存储器阵列的元件的机构。 在说明性应用中，存储器是动态随机存取存储器，并且本发明的系统适于提供已经存储或将要存储数据的那些DRAM存储器元件的选择性刷新。 这允许使用有利的DRAM存储器元件，同时使其功耗最小化。 因此，DRAM存储器元件的实用性扩展到各种功率敏感应用，包括蜂窝电话和移动计算。

    CHANNEL STATE COMPUTATION FOR ENHANCED CARRIER AGGREGATION
    5.
    发明申请
    CHANNEL STATE COMPUTATION FOR ENHANCED CARRIER AGGREGATION 审中-公开
    用于增强载波聚合的信道状态计算

    公开(公告)号：WO2017052833A1

    公开(公告)日：2017-03-30

    申请号：PCT/US2016/046736

    申请日：2016-08-12

    Applicant: QUALCOMM INCORPORATED

    Inventor： SUBRAHMANYA, Parvathanathan ,  SHEN, Qiang ,  KHANDEKAR, Aamod, Dinkar ,  MOTAMED, Mariam ,  CHEN, Wanshi ,  PAN, Hanfang ,  MATHEW, Deepak

    IPC: H04L5/00 ,  H04L1/00 ,  H04W72/12 ,  H04W24/10

    CPC classification number: H04W24/10 ,  H04L1/0026 ,  H04L1/0027 ,  H04L1/0029 ,  H04L5/001 ,  H04L5/0048 ,  H04L5/0057 ,  H04W8/22

    Abstract: Methods, systems, and devices for wireless communication are described. A user equipment (UE) utilizing enhanced carrier aggregation (eCA) may identify a limit to the number of channel state feedback (CSF) processes it is capable of supporting. The UE may transmit an indication of this limit to a base station, which may configure the UE for channel state reporting, and send channel state reporting triggers according to the indicated limit. The UE's determination of the limit to the number of CSF processes may be based on various transmit or receive antenna configurations. A single trigger may correspond to reports covering multiple subframes and/or component carriers. The base station may also arrange the channel state reporting configuration to reduce the peak number of channel state reports that the UE processes during each subframe. The UE may also determine that a number of channel state processes needed to support channel state reporting in a subframe exceeds its capacity. The UE may then prioritize the channel state processes and/or may transmit one or more non-current reports.

    Abstract translation: 描述了用于无线通信的方法，系统和设备。 利用增强的载波聚合（eCA）的用户设备（UE）可以识别其能够支持的信道状态反馈（CSF）过程的数量的限制。 UE可以向基站发送该限制的指示，该基站可以将UE配置为信道状态报告，并根据指示的限制发送信道状态报告触发。 UE对CSF过程数量的限制的确定可以基于各种发射或接收天线配置。 单个触发器可以对应于覆盖多个子帧和/或分量载波的报告。 基站还可以布置信道状态报告配置以减少在每个子帧期间UE处理的信道状态报告的峰值数量。 UE还可以确定在子帧中支持信道状态报告所需的信道状态过程的数量超过其容量。 然后，UE可以优先化信道状态过程和/或可以发送一个或多个非当前报告。

    SCALABLE SCHEDULER ARCHITECTURE FOR CHANNEL DECODING
    6.
    发明申请
    SCALABLE SCHEDULER ARCHITECTURE FOR CHANNEL DECODING 审中-公开
    用于信道解码的可调度调度器架构

    公开(公告)号：WO2011143305A1

    公开(公告)日：2011-11-17

    申请号：PCT/US2011/036059

    申请日：2011-05-11

    Applicant: QUALCOMM Incorporated ,  CHANG, Wei-Hsin ,  PAN, Hanfang ,  HOWARD, Michael Alexander ,  WU, Wenqing ,  FUCHS, Robert Jason

    Inventor： CHANG, Wei-Hsin ,  PAN, Hanfang ,  HOWARD, Michael Alexander ,  WU, Wenqing ,  FUCHS, Robert Jason

    IPC: H04L1/00

    CPC classification number: H04L1/0052

    Abstract: Certain aspects of the present disclosure relate to a method for processing wireless communications. According to one aspect, a processing unit may receive a plurality of code blocks of a transport block and schedule the plurality of code blocks to be decoded in parallel with a plurality of decoders. Each decoder decodes at least one code block as an independent tasks. The processing unit further collects the decoded information bits from the plurality of decoders and forwards the collected decoded information bits for further processing. In one aspect, the processing unit includes an output agent to temporarily store the decoded information bits while waiting for all code blocks of the transport block to be decoded.

    Abstract translation: 本公开的某些方面涉及一种用于处理无线通信的方法。 根据一个方面，处理单元可以接收传输块的多个码块，并且与多个解码器并行地调度要解码的多个码块。 至少一个解码器解码至少一个代码块作为独立任务。 处理单元进一步从多个解码器中收集解码的信息比特，并且转发所收集的解码信息比特用于进一步处理。 一方面，处理单元包括一个输出代理，用于临时存储解码的信息位，同时等待传输块的所有代码块被解码。

    HDLC HARDWARE ACCELERATOR
    7.
    发明申请
    HDLC HARDWARE ACCELERATOR 审中-公开

    公开(公告)号：WO2003073726A3

    公开(公告)日：2003-09-04

    申请号：PCT/US2003/006330

    申请日：2003-02-27

    Applicant: QUALCOMM INCORPORATED

    Inventor： ABROL, Nischal ,  LIN, Jian ,  PAN, Hanfang ,  TURNER, Simon

    IPC: H04L29/06

    Abstract: An HDLC accelerator includes a deframer and framer to respectively accelerate the deframing and framing processes for PPP packets. The deframer includes an input interface unit, a detection unit, a conversion unit, and an output interface unit. The input interface unit receives a packet of data to be deframed. The detection unit evaluates each data byte to detect for special bytes (e.g., flag, escape, and invalid bytes). The conversion unit deframes the received data by removing flag and escape bytes, "un-escaping" the data byte following each escape byte, providing a header word for each flag byte, and checking each deframed packet based on a frame check sequence (FCS) value associated with the packet. The output interface unit provides deframed data and may further perform byte alignment in providing the deframed data. A state control unit provides control signals indicative of specific tasks to be performed for deframing.

    METHOD AND APPARATUS FOR PARALLEL DE-INTERLEAVING OF LTE INTERLEAVED DATA
    8.
    发明申请
    METHOD AND APPARATUS FOR PARALLEL DE-INTERLEAVING OF LTE INTERLEAVED DATA 审中-公开
    用于LTE交互数据并行去交织的方法和装置

    公开(公告)号：WO2011143259A1

    公开(公告)日：2011-11-17

    申请号：PCT/US2011/035978

    申请日：2011-05-10

    Applicant: QUALCOMM Incorporated ,  WU, Wenqing ,  PAN, Hanfang ,  HOWARD, Michael A.

    Inventor： WU, Wenqing ,  PAN, Hanfang ,  HOWARD, Michael A.

    IPC: H03M13/27

    CPC classification number: H03M13/2775 ,  H03M13/2739 ,  H03M13/275 ,  H03M13/6525 ,  H03M13/6566

    Abstract: A wireless communication signal in Long Term Evolution (LTE) may be interleaved in a manner which permits a partitioning of a received inter-column bit- reversed interleaved code block for improved de-interleaving. The code block may be divided into equal subportions which may be simultaneously de-interleaved both forward and backward, and in parallel with other subportions. An even number of subportions may be provided. Dividing a received code block in this manner may improve de-interleaving performance.

    Abstract translation: 长期演进（LTE）中的无线通信信号可以以允许对接收到的列间比特反转交织码块进行分区以改进解交织的方式进行交织。 码块可以被划分成相等的子部分，其可以同时前向和后向解交织，并且与其他子部分并行。 可以提供偶数个子部分。 以这种方式分割接收到的码块可以提高去交织性能。

    EFFICIENT ZADOFF-CHU SEQUENCE GENERATION
    9.
    发明申请
    EFFICIENT ZADOFF-CHU SEQUENCE GENERATION 审中-公开
    有效的ZADOFF-CHU序列生成

    公开(公告)号：WO2011127007A1

    公开(公告)日：2011-10-13

    申请号：PCT/US2011/031166

    申请日：2011-04-05

    Applicant: QUALCOMM Incorporated ,  GAAL, Peter ,  FUCHS, Robert J. ,  WEI, Yongbin ,  LIU, Ke ,  PAN, Hanfang ,  MALLADI, Durga Prasad ,  MACEK, Daniel T.

    Inventor： GAAL, Peter ,  FUCHS, Robert J. ,  WEI, Yongbin ,  LIU, Ke ,  PAN, Hanfang ,  MALLADI, Durga Prasad ,  MACEK, Daniel T.

    IPC: H04J13/00 ,  H04J13/14

    CPC classification number: H04J13/0059 ,  H04J13/14

    Abstract: Efficient apparatus and method for Zadoff-Chu ("Chu") sequence generation avoids additional processing and hardware complexity of conventional quadratic generating formula followed by Discrete Fourier Transform (DFT) with a reference signal generator that produces both a Zadoff-Chu sequence and its DFT. In the wireless communication system (e.g., Long Term Evolution (LTE) system), Chu sequences are extensively used, especially in the uplink (UL). Because of the single carrier operating mode, transmitting a Chu sequence in principle involves a succession of generating that sequence, performing a DFT operation and then an IFFT operation. Assuming that the sequence length is N, the initial sequence generation requires 2N multiplications and the DFT requires more than Nlog2(N) multiplications. Given the frequent processing of Chu sequences, this would represent a complexity burden. The invention makes it possible to perform the sequence generation and DFT steps without any multiplication operation, except for possibly calculating certain initial parameters.

    Abstract translation: 用于Zadoff-Chu（“Chu”）序列生成的高效装置和方法避免了传统二次生成公式的附加处理和硬件复杂性，随后是具有产生Zadoff-Chu序列及其DFT的参考信号发生器的离散傅里叶变换（DFT） 。 在无线通信系统（例如，长期演进（Long Term Evolution，LTE）系统）中，尤其在上行链路（UL）中广泛使用了Chu序列。 由于单载波操作模式，原则上发送Chu序列涉及一系列生成该序列，执行DFT操作，然后进行IFFT操作。 假设序列长度为N，则初始序列生成需要2N次乘法，并且DFT需要多于Nlog2（N）个乘法。 鉴于Chu序列的频繁处理，这将代表一个复杂的负担。 除了可能计算某些初始参数之外，本发明使得可以执行没有任何乘法运算的序列生成和DFT步骤。

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