公开(公告)号：WO2017053086A1

公开(公告)日：2017-03-30

申请号：PCT/US2016/050961

申请日：2016-09-09

Applicant: QUALCOMM INCORPORATED

Inventor： LE, Hien, Minh ,  TRUONG, Thuong, Quang ,  XU, Kun ,  SUBRAMANIAM GANASAN, Jaya, Prakash ,  RAMIREZ, Cesar, Aaron

IPC: G06F12/0815 ,  G06F9/52 ,  G06F12/0831

CPC classification number: G06F12/0831 ,  G06F9/524 ,  G06F12/0815 ,  G06F12/0833 ,  G06F13/16 ,  G06F13/4027 ,  G06F13/42 ,  G06F2212/1008 ,  G06F2212/621

Abstract: Aspects disclosed herein include avoiding deadlocks in processor-based systems employing retry and in-order-response non-retry bus coherency protocols. In this regard, an interface bridge circuit is communicatively coupled to a first core device that implements a retry bus coherency protocol, and a second core device that implements an in-order-response non-retry bus coherency protocol. The interface bridge circuit receives a snoop command from the first core device, and forwards the snoop command to the second core device. While the snoop command is pending, the interface bridge circuit detects a potential deadlock condition between the first core device and the second core device. In response to detecting the potential deadlock condition, the interface bridge circuit is configured to send a retry response to the first core device. This enables the first core device to continue processing, thereby eliminating the potential deadlock condition.

Abstract translation: 本文公开的方面包括在采用重试和有序响应非重试总线一致性协议的基于处理器的系统中避免死锁。 在这方面，接口桥电路通信地耦合到实现重试总线一致性协议的第一核心设备，以及实现按顺序响应非重试总线一致性协议的第二核心设备。 接口桥电路从第一核心设备接收窥探命令，并将侦听命令转发给第二核心设备。 当snoop命令待处理时，接口桥电路检测第一核心设备和第二核心设备之间的潜在死锁状态。 响应于检测到潜在的死锁状态，接口桥电路被配置为向第一核心设备发送重试响应。 这使得第一核心设备能够继续处理，从而消除潜在的死锁状况。

公开(公告)号：WO2017053087A1

公开(公告)日：2017-03-30

申请号：PCT/US2016/050987

申请日：2016-09-09

Applicant: QUALCOMM INCORPORATED

Inventor： XU, Kun ,  TRUONG, Thuong, Quang ,  SUBRAMANIAM GANASAN, Jaya, Prakash ,  LE, Hien, Minh ,  RAMIREZ, Cesar, Aaron

IPC: G06F12/0831

CPC classification number: G06F12/0815 ,  G06F12/0831 ,  G06F2212/1024 ,  G06F2212/1028 ,  G06F2212/621 ,  Y02D10/13

Abstract: Maintaining cache coherency using conditional intervention among multiple master devices is disclosed. In one aspect, a conditional intervention circuit is configured to receive intervention responses from multiple snooping master devices. To select a snooping master device to provide intervention data, the conditional intervention circuit determines how many snooping master devices have a cache line granule size the same as or larger than a requesting master device. If one snooping master device has a same or larger cache line granule size, that snooping master device is selected. If more than one snooping master device has a same or larger cache line granule size, a snooping master device is selected based on an alternate criteria. The intervention responses provided by the unselected snooping master devices are canceled by the conditional intervention circuit, and intervention data from the selected snooping master device is provided to the requesting master device.

Abstract translation: 公开了使用多个主设备之间的条件干预来维护高速缓存一致性。 在一个方面，条件干预电路被配置为从多个窥探主设备接收干预响应。 为了选择窥探主设备来提供干预数据，条件干预电路确定有多少个窥探主设备具有与请求主设备相同或更大的高速缓存线粒度大小。 如果一个侦听主设备具有相同或更大的缓存线粒度大小，则选择该窥探主设备。 如果多个侦听主设备具有相同或更大的缓存线粒度大小，则会根据备用标准选择侦听主设备。 由未选择的窥探主设备提供的干预响应由条件干预电路取消，并且来自所选窥探主设备的干预数据被提供给请求主设备。