公开(公告)号：WO2016209733A1

公开(公告)日：2016-12-29

申请号：PCT/US2016/038146

申请日：2016-06-17

Applicant: QUALCOMM INCORPORATED

Inventor： YIFRACH, Shaul; Yohai ,  GIL, Amit ,  PANIAN, James; Lionel ,  ROSENBERG, Ofer

IPC: G06F12/0806 ,  G06F15/167

CPC classification number: G06F13/4282 ,  G06F12/0828 ,  G06F12/1441 ,  G06F13/4022 ,  G06F15/167 ,  G06F21/00 ,  G06F2212/621 ,  G06F2213/0026

Abstract: Coherency driven enhancements to a PCIe transaction layer are disclosed. In an exemplary aspect, a coherency agent is added to a PCIe system to support a relaxed consistency model for use of memory therein. In particular, endpoints can request ownership of portions of the memory to read from and write to the memory. The coherency agent assigns an address range including the requested portions. The requesting endpoint copies the contents of the memory corresponding to the assigned address range into local endpoint memory to perform read and write operations locally. The owning endpoint may provide an updated snapshot of the copied memory contents upon request. At completion of use of the copied memory contents, or upon request from the coherency agent, ownership of the address range reverts back to the root complex, and the endpoint sends the updated contents back to the address range in the system memory element.

Abstract translation: 公开了对PCIe事务层的一致性驱动的增强。 在示例性方面，将一致性代理添加到PCIe系统以支持用于其中的存储器的松弛一致性模型。 特别地，端点可以请求存储器的一部分的所有权从存储器读取和写入存储器。 一致性代理分配包括请求部分的地址范围。 请求端点将对应于分配的地址范围的内存的内容复制到本地端点存储器中，以在本地执行读写操作。 所拥有的端点可以根据请求提供复制的存储器内容的更新的快照。 在完成使用复制的存储器内容时，或者根据来自一致性代理的请求，地址范围的所有权返回到根复合体，并且端点将更新的内容发送回系统存储器元件中的地址范围。

公开(公告)号：WO2016209730A1

公开(公告)日：2016-12-29

申请号：PCT/US2016/038120

申请日：2016-06-17

Applicant: QUALCOMM INCORPORATED

Inventor： ROSENBERG, Ofer ,  GIL, Amit ,  PANIAN, James; Lionel ,  PATEL, Piyush ,  YIFRACH, Shaul; Yohai

IPC: G06F13/24

CPC classification number: G06F13/24 ,  G06F13/4282

Abstract: Extended message signaled interrupts (MSI) data are disclosed. In one aspect, MSI bits are modified to include a system level identifier. In an exemplary aspect, an upper sixteen bits of the MSI message data are modified to be the system level identifier. By providing the system level identifier within the MSI message data, an interrupt controller can verify the interrupt source.

Abstract translation: 公开了扩展消息信号中断（MSI）数据。 在一个方面，MSI比特被修改为包括系统级标识符。 在示例性方面，MSI消息数据的高16位被修改为系统级标识符。 通过在MSI消息数据内提供系统级标识符，中断控制器可以验证中断源。

公开(公告)号：WO2017165657A1

公开(公告)日：2017-09-28

申请号：PCT/US2017/023832

申请日：2017-03-23

Applicant: QUALCOMM INCORPORATED

Inventor： KLACAR, Neven ,  KRISHNA, Murali ,  MAHESHWARI, Shailesh ,  RANJAN, Suyash ,  ROSENBERG, Ofer

IPC: G06F13/42 ,  G06F1/32

Abstract: Link speed control systems for power optimization are disclosed.In one aspect, a communication link adjusts a data transfer speed based on link utilization levels.In a second exemplary aspect, one or more conditions affecting a link speed are weighted and collectively evaluated to determine an efficient or optimal link speed. By adjusting the link speed in this fashion, lower link speeds may be used, and net power savings may be effectuated.

Abstract translation: 公开了用于功率优化的链路速度控制系统。一方面，通信链路基于链路利用率水平来调整数据传输速度。在第二示例性方面中，影响链路速度的一个或多个条件 被加权并且被共同评估以确定有效的或最优的链路速度。 通过以这种方式调整链接速度，可以使用较低的链接速度，并且可以实现净节能。

公开(公告)号：WO2021178704A1

公开(公告)日：2021-09-10

申请号：PCT/US2021/020925

申请日：2021-03-04

Applicant: QUALCOMM INCORPORATED

Inventor： GADELRAB, Serag ,  CHATHA, Karamvir ,  ROSENBERG, Ofer

IPC: G06N3/063

Abstract: Certain aspects of the present disclosure provide techniques for adaptively executing machine learning models on a computing device. An example method generally includes receiving weight information for a machine learning model to be executed on a computing device. The received weight information is reduced into quantized weight information having a reduced bit size relative to the received weight information. First inferences using the machine learning model and the received weight information, and second inferences are performed using the machine learning model and the quantized weight information. Results of the first and second inferences are compared, it is determined that results of the second inferences are within a threshold performance level of results of the first inferences, and based on the determination, one or more subsequent inferences are performed using the machine learning model and the quantized weight information.

公开(公告)号：WO2018080774A1

公开(公告)日：2018-05-03

申请号：PCT/US2017/055726

申请日：2017-10-09

Applicant: QUALCOMM INCORPORATED

Inventor： YIFRACH, Shaul, Yohai ,  GIL, Amit ,  PANIAN, James, Lionel ,  ROSENBERG, Ofer ,  WIETFELDT, Richard, Dominic

IPC: G06F13/42 ,  G06F13/40

CPC classification number: G06F1/3253 ,  G06F13/4072 ,  G06F13/4273 ,  G06F13/4291 ,  H01L23/291 ,  H04L49/40 ,  Y02D10/151

Abstract: A replacement physical layer (PHY) for low-speed Peripheral Component Interconnect (PCI) Express (PCIe) systems is disclosed. In one aspect, an analog PHY of a conventional PCIe system is replaced with a digital PHY. The digital PHY is coupled to a media access control (MAC) logic by a PHY interface for PCIe (PIPE) directly. In further exemplary aspects, the digital PHY may be a complementary metal oxide semiconductor (CMOS) PHY that includes a serializer and a deserializer. Replacing the analog PHY with the digital PHY allows entry and exit from low-power modes to occur much quicker, resulting in substantial power savings and reduced latency. Because the digital PHY is operable with low-speed communication, the digital PHY can maintain sufficient bandwidth that communication is not unnecessarily impacted by digital logic of the digital PHY.

Abstract translation: 公开了用于低速外围组件互连（PCI）快速（PCIe）系统的替代物理层（PHY）。 在一个方面，常规PCIe系统的模拟PHY被数字PHY替换。 数字PHY通过用于PCIe（PIPE）的PHY接口直接耦合到媒体访问控制（MAC）逻辑。 在进一步的示例性方面，数字PHY可以是包括串行器和解串器的互补金属氧化物半导体（CMOS）PHY。 用数字PHY替代模拟PHY允许更快地进入和退出低功耗模式，从而大幅节省功耗并缩短延迟时间。 由于数字PHY可通过低速通信进行操作，因此数字PHY可以保持足够的带宽，通信不会受到数字PHY的数字逻辑不必要的影响。

公开(公告)号：WO2016209568A1

公开(公告)日：2016-12-29

申请号：PCT/US2016/035155

申请日：2016-06-01

Applicant: QUALCOMM INCORPORATED

Inventor： ROSENBERG, Ofer ,  GIL, Amit ,  PANIAN, James; Lionel ,  PATEL, Piyush ,  YIFRACH, Shaul; Yohai

IPC: G06F13/42

CPC classification number: G06F13/4282 ,  G06F13/1673 ,  G06F13/4022 ,  G06F2213/0026

Abstract: A PCIe system includes a host system (304) and at least one PCIe endpoint (302). The PCIe endpoint is configured to determine one or more transaction-specific attributes that can improve efficiency and performance of a predefined host transaction. The PCIe endpoint encodes the transaction-specific attributes in a transaction layer packet (TLP) prefix of at least one PCIe TLP and provides the PCIe TLP to the host system. A PCIe root complex (316) in the host system is configured to detect and extract the transaction-specific attributes from the TLP prefix of the PCIe TLP received from the PCIe endpoint. By communicating the transaction-specific attributes in the TLP prefix of the PCIe TLP, it is possible to improve efficiency and performance of the PCIe system without violating the existing PCIe standard.

Abstract translation: PCIe系统包括主机系统（304）和至少一个PCIe端点（302）。 PCIe端点配置为确定可以提高预定义主机事务的效率和性能的一个或多个特定于事务的属性。 PCIe端点对至少一个PCIe TLP的事务层分组（TLP）前缀中的事务特定属性进行编码，并将PCIe TLP提供给主机系统。 主机系统中的PCIe根组合（316）被配置为从PCIe端点接收的PCIe TLP的TLP前缀中检测并提取特定于事务的属性。 通过传递PCIe TLP的TLP前缀中的特定于交易的属性，可以在不违反现有PCIe标准的情况下提高PCIe系统的效率和性能。