公开(公告)号：WO2016048471A1

公开(公告)日：2016-03-31

申请号：PCT/US2015/045020

申请日：2015-08-13

Applicant: QUALCOMM INCORPORATED

Inventor： WIETFELDT, Richard, Dominic ,  CHRISIKOS, George ,  WILEY, George, Alan

IPC: H04B1/12 ,  H04B15/02 ,  H04W88/02

CPC classification number: H04B15/02 ,  H04B1/123 ,  H04B17/23 ,  H04W72/082

Abstract: Aspects of adjusting application parameters for interference mitigation are disclosed. In one aspect, a computing device is provided that employs a control system configured to detect and mitigate electromagnetic interference (EMI) generated within the computing device. More specifically, the control system is configured to detect possible EMI conditions and adjust parameters within the computing device to mitigate such EMI. In this manner, the computing device includes an aggressor application and a victim receiver. The control system is configured to analyze performance tradeoffs based on an acceptable performance level of the aggressor application and the performance degradation experienced by the victim receiver. Based on such analysis, the control system is configured to adjust parameters associated with the aggressor application to mitigate the EMI. Thus, the control system provides designers with an additional tool that may reduce the performance degradation of the victim receiver attributable to the EMI.

Abstract translation: 公开了调整用于干扰减轻的应用参数的方面。 在一个方面，提供了一种计算设备，其采用配置成检测和减轻在计算设备内产生的电磁干扰（EMI）的控制系统。 更具体地，控制系统被配置为检测可能的EMI条件并且调整计算设备内的参数以减轻这样的EMI。 以这种方式，计算设备包括攻击者应用和受害者接收器。 控制系统被配置为基于攻击者应用的可接受的性能水平和受害者接收器所经历的性能下降来分析性能权衡。 基于这种分析，控制系统被配置为调整与侵略者应用相关联的参数以减轻EMI。 因此，控制系统为设计人员提供了一种附加工具，可以降低由于EMI引起的受害接收机的性能下降。

公开(公告)号：WO2016144816A1

公开(公告)日：2016-09-15

申请号：PCT/US2016/021047

申请日：2016-03-04

Applicant: QUALCOMM INCORPORATED

Inventor： MISHRA, Lalan, Jee ,  WIETFELDT, Richard, Dominic ,  PANIAN, James, Lionel ,  WILEY, George, Alan ,  GIL, Amit

IPC: G06F1/32

CPC classification number: G06F11/3051 ,  G06F1/3209 ,  G06F1/3278 ,  G06F9/4418 ,  G06F11/3041 ,  G06F15/17 ,  G06F15/7807 ,  Y02D10/157

Abstract: System, methods, and apparatuses are described that facilitate a first device to transmit/retransmit a message to a second device. The first device transmits a first message to the second device. The first device then receives a second message and identifies a bit of the second message indicating an originator of the second message. If the bit indicates the first device as the originator of the second message, then the second message is an echo of the first message. Reception of the echo indicates that the second device is in a sleep state. Accordingly, the first device waits for the second device to wake and retransmits the first message to the second device to ensure that any packets lost during the original transmission of the first message (when the second device was asleep) are now retransmitted while the second device is known to be awake.

Abstract translation: 描述了便于第一设备向第二设备发送/重发消息的系统，方法和设备。 第一设备向第二设备发送第一消息。 然后，第一设备接收第二消息并且识别指示第二消息的发起者的第二消息的位。 如果该比特指示第一个设备作为第二个消息的发起者，则第二个消息是第一个消息的回应。 回波的接收指示第二设备处于睡眠状态。 因此，第一设备等待第二设备唤醒并将第一消息重新发送到第二设备，以确保在第一消息的原始传输期间（当第二设备睡着时）丢失的任何分组现在在第二设备 已知醒来。

公开(公告)号：WO2015200292A1

公开(公告)日：2015-12-30

申请号：PCT/US2015/037132

申请日：2015-06-23

Applicant: QUALCOMM INCORPORATED

Inventor： PANDEY, Shree, Krishna ,  KUNDU, Arun, Chandra ,  WILEY, George, Alan ,  LEE, Chulkyu

IPC: H04L25/02

CPC classification number: H04L7/0041 ,  H04B3/00 ,  H04B3/462 ,  H04B3/542 ,  H04L25/0264

Abstract: In a multi-wire channel that includes at least three wires, each unique wire pair of the multi-wire channel has approximately the same signal propagation time. In this way, jitter can be mitigated in the multi-wire channel for signaling where, for a given data transfer, a differential signal is transmitting on a particular pair of the wires and every other wire is floating. In some implementations, matching of the signal propagation times involves providing additional delay for at least one of the wires. The additional delay is provided using passive signal delay techniques and/or active signal delay techniques.

Abstract translation: 在包括至少三条电线的多线通道中，多线通道的每条唯一的线对具有大致相同的信号传播时间。 以这种方式，可以在用于信令的多线信道中减轻抖动，其中对于给定的数据传输，差分信号在特定的一对导线上传输，并且每隔一个线路浮动。 在一些实现中，信号传播时间的匹配涉及为至少一条电线提供额外的延迟。 使用无源信号延迟技术和/或有源信号延迟技术来提供额外的延迟。

公开(公告)号：WO2006105331A3

公开(公告)日：2006-10-05

申请号：PCT/US2006/011743

申请日：2006-03-31

Applicant: QUALCOMM INCORPORATED ,  JACOBS, Paul, E. ,  WILEY, George, Alan ,  ANTONIO, Franklin, Peter

Inventor： JACOBS, Paul, E. ,  WILEY, George, Alan ,  ANTONIO, Franklin, Peter

IPC: H04B1/38

Abstract: A mobile electronic device (102) includes an earphone/microphone port (104), an I/O circuit to receive a modulated data signal from data input devices via the earphone/microphone port (104), and a processor unit (204) programmed to extract data from the modulated data signal. The processor unit (or the I/O circuit) detects connection of a device to an earphone/microphone connector of the mobile electronic device (102) and determines whether the connected device is a data input device. If the connected device is a data input device (106), the processor unit (204) is programmed to extract data from modulated data signals generated by data input device (106).

公开(公告)号：WO2003023587A2

公开(公告)日：2003-03-20

申请号：PCT/US2002/028461

申请日：2002-09-06

Applicant: QUALCOMM, INCORPORATED

Inventor： ZOU, Qiuzhen ,  WILEY, George, Alan ,  STEELE, Brian

IPC: G06F3/00

CPC classification number: H04L25/45 ,  G06F3/14 ,  G09G5/006 ,  G09G5/06 ,  G09G2370/045 ,  G09G2370/10 ,  G09G2370/16 ,  H04M1/72527 ,  H04N19/46 ,  Y02D70/26

Abstract: A data Interface for transferring digital data between a host and a client over a communication path using packet structures linked together to form a communication protocol for communicating a pre-selected set of digital control and presentation data. The signal protocol is used by link controllers configured to generate, transmit, and receive packets forming the communications protocol, and to form digital data into one or more types of data packets, with at least one residing in the host device and being coupled to the client through the communications path. The interface provides a cost-effective, low power, bi-directional, high-speed data transfer mechanism over a short-range "serial" type data link, which lends itself to implementation with miniature connectors and thin flexible cables which are especially useful in connecting display elements such as wearable micro-displays to portable computers and wireless communication devices.

Abstract translation: 数据接口，用于使用链接在一起的分组结构在通信路径上在主机和客户机之间传送数字数据，以形成用于传送预先选择的一组数字控制和演示数据的通信协议。 信号协议由链路控制器使用，所述链路控制器被配置为生成，发送和接收形成通信协议的分组，并且将数字数据形成为一种或多种类型的数据分组，其中至少一个驻留在主机设备中并且耦合到 客户端通过通信路径。 该接口通过短距离“串行”接口提供了成本低，功耗低，双向，高速的数据传输机制。 型数据链路，它适用于微型连接器和薄型柔性电缆，这些连接器尤其适用于将可穿戴微型显示器等显示器元件连接到便携式计算机和无线通信设备。

公开(公告)号：WO2019139729A1

公开(公告)日：2019-07-18

申请号：PCT/US2018/065711

申请日：2018-12-14

Applicant: QUALCOMM INCORPORATED

Inventor： WILEY, George, Alan

IPC: G06F13/42 ,  H04L12/40

Abstract: Systems, methods and apparatus are described that facilitate transmission of data between two devices within an electronic apparatus, A data transfer method includes receiving from a three-wire interface, a first packet of data encoded in a first sequence of symbols representing transitions in signaling state of the three wires, and transmitting on the three-wire interface, a second packet of data encoded in a second sequence of symbols representing transitions in signaling state of the three wires. The first sequence of symbols may include up to five types of symbol. The second sequence of symbols may include two or three types of symbol

公开(公告)号：WO2017196875A1

公开(公告)日：2017-11-16

申请号：PCT/US2017/031802

申请日：2017-05-09

Applicant: QUALCOMM INCORPORATED

Inventor： MISHRA, Lalan, Jee ,  WIETFELDT, Richard, Dominic ,  WILEY, George, Alan

IPC: G06F13/38

CPC classification number: G06F13/4286 ,  G06F13/38 ,  G06F13/385 ,  G06F13/387 ,  G06F13/4022 ,  G06F13/4068 ,  G06F13/4213

Abstract: Systems, methods, and apparatus for line multiplexed serial interfaces are disclosed. A method performed by a transmitting device includes asserting a stop condition on a wire of a serial data link by driving the wire to a first voltage level for a first period of time that is less than a duration of the stop condition, monitoring the wire after the first period of time, determining that flow-control has been asserted when the wire remains at a second voltage level for a second period of time that exceeds a minimum period of time defined for flow-control pulses and after the first period of time has elapsed, refraining from transmitting data on the wire while flow-control is asserted, and transmitting data on the wire when flow-control is de-asserted.

Abstract translation: 公开了用于线路多路复用串行接口的系统，方法和设备。 由发送设备执行的方法包括：通过在小于停止条件的持续时间的第一时间段内将导线驱动至第一电压电平，在串行数据链路的导线上断言停止条件，在导线之后监测导线 在所述第一时间段内，确定当所述导线保持在第二电压水平持续超过为流量控制脉冲定义的最小时间段的第二时间段时并且在所述第一时间段之后已经断定流量控制 经过的时间，在流控制断言时避免在线上传输数据，并且当流控制被解除断言时在线上传输数据。

公开(公告)号：WO2009073250A2

公开(公告)日：2009-06-11

申请号：PCT/US2008/063109

申请日：2008-05-08

Applicant: QUALCOMM INCORPORATED ,  STEELE, Brian ,  WILEY, George, Alan ,  SHEKHAR, Shashank

Inventor： STEELE, Brian ,  WILEY, George, Alan ,  SHEKHAR, Shashank

IPC: H04L12/56 ,  H04N7/24

CPC classification number: H04L69/22 ,  H04L69/18 ,  H04W80/02

Abstract: A packet structure for a Mobile Display Digital Interface (MDDI) includes a flexible sub-frame length to efficiently transmit large packets. A windowless video stream packet avoids repetitive transmissions of video packets when some parameters are unchanged, saving bandwidth. An enhanced reverse encapsulation packet combines the feature of a separate round trip delay packet with a separate reverse encapsulation packet. A link freeze is used to halt a transmission of a data stream at any point in the transmission and resume the transmission by a host.

Abstract translation: 用于移动显示数字接口（MDDI）的分组结构包括有效传输大分组的灵活子帧长度。 当一些参数不变时，无窗口视频流数据包避免视频数据包的重复传输，从而节省带宽。 增强的反向封装分组将单独的往返延迟分组的特征与单独的反向封装分组相结合。 链路冻结用于在传输中的任何点停止数据流的传输，并由主机恢复传输。

公开(公告)号：WO2017044247A1

公开(公告)日：2017-03-16

申请号：PCT/US2016/046728

申请日：2016-08-12

Applicant: QUALCOMM INCORPORATED

Inventor： WIETFELDT, Richard, Dominic ,  LECLERCQ, Maxime ,  WILEY, George, Alan

IPC: G06F13/38 ,  H04L12/26

CPC classification number: G06F13/4027 ,  G06F13/385 ,  G06F13/4068 ,  H04L43/0817

Abstract: Unified systems and methods for interchip and intrachip node communication are disclosed. In one aspect, a single unified low-speed bus is provided that connects each of the chips within a computing device. The chips couple to the bus through a physical layer interface and associated gateway. The gateway includes memory that stores a status table summarizing statuses for every node in the interface fabric. As nodes experience state changes, the nodes provide updates to associated local gateways. The local gateways then message, using a scout message, remote gateways with information relating to the state changes. When a first node is preparing a signal to a second node, the first node checks the status table at the associated local gateway to determine a current status for the second node. Based on the status of the second node, the first node may send the message or take other appropriate action.

Abstract translation: 公开了用于芯片间和节点间通信的统一系统和方法。 在一个方面，提供了连接计算设备内的每个芯片的单个统一的低速总线。 芯片通过物理层接口和相关网关耦合到总线。 网关包括存储状态表的内存，其汇总接口结构中每个节点的状态。 当节点经历状态改变时，节点向相关联的本地网关提供更新。 然后，本地网关使用侦察器消息来发送具有与状态改变有关的信息的远程网关。 当第一节点准备到第二节点的信号时，第一节点检查相关联的本地网关处的状态表以确定第二节点的当前状态。 基于第二节点的状态，第一节点可以发送消息或采取其他适当的动作。

公开(公告)号：WO2009158541A1

公开(公告)日：2009-12-30

申请号：PCT/US2009/048720

申请日：2009-06-25

Applicant: QUALCOMM INCORPORATED ,  LEE, ChulKyu ,  WILEY, George, Alan

Inventor： LEE, ChulKyu ,  WILEY, George, Alan

IPC: H03M9/00

CPC classification number: H04Q11/04 ,  H03M9/00

Abstract: A deserializer circuit and method convert a serial bit stream into a parallel bit stream according to a parallel grouping. The deserializer and method include alternatingly demultiplexing a serial data stream into first and second bit streams. The first and second bit streams are respectively serially shifted along a first plurality of shift registers and a second plurality of shift registers. A first portion of the first bit stream in the first plurality of shift registers is selected and a second portion of the second bit stream in the second plurality of shift registers is also selected. A parallel group of data in a parallel data stream is formed from the first and second portions.

Abstract translation: 解串器电路和方法根据并行分组将串行比特流转换成并行比特流。 解串器和方法包括将串行数据流交替解复用为第一和第二位流。 第一和第二比特流分别沿着第一多个移位寄存器和第二多个移位寄存器串行移位。 选择第一多个移位寄存器中的第一比特流的第一部分，并且还选择第二多个移位寄存器中的第二比特流的第二部分。 并行数据流中的并行数据组由第一和第二部分形成。