公开(公告)号：WO2015112609A1

公开(公告)日：2015-07-30

申请号：PCT/US2015/012260

申请日：2015-01-21

Applicant: RADIANT TECHNOLOGIES, INC. ,  EVANS, Joseph, T.

Inventor： EVANS, Joseph, T.

IPC: H03K21/08

CPC classification number: H03K21/08 ,  G11C11/221 ,  H03K23/766

Abstract: A counter that can include a plurality of count stages is disclosed. Each count stage includes a ferroelectric capacitor characterized by first and second polarization states, a variable impedance element, reset and count ports and a detector. The variable impedance element has an impedance between first and second switch terminals that is determined by a signal on a control terminal, the ferroelectric capacitor being connected between the control terminal and the first switch terminal. A reset signal coupled to the control terminal causes the ferroelectric capacitor to be polarized in the first polarization state. The count port is configured to receive pulses to be counted, the count port being connected to the first switch terminal by a conductive load. The detector generates a count complete signal if a potential on the first terminal exceeds a threshold value while the count port is receiving one of the pulses.

Abstract translation: 公开了可以包括多个计数级的计数器。 每个计数级包括由第一和第二极化状态表征的铁电电容器，可变阻抗元件，复位和计数端口以及检测器。 可变阻抗元件具有由控制端子上的信号确定的第一和第二开关端子之间的阻抗，铁电电容器连接在控制端子和第一开关端子之间。 耦合到控制端子的复位信号使铁电电容器在第一偏振状态下被极化。 计数端口被配置为接收待计数的脉冲，计数端口通过导电负载连接到第一开关端子。 如果计数端口正在接收到其中一个脉冲，则第一端子上的电位超过阈值时，检测器产生计数完成信号。

公开(公告)号：WO2014008211A1

公开(公告)日：2014-01-09

申请号：PCT/US2013/048982

申请日：2013-07-01

Applicant: RADIANT TECHNOLOGIES, INC. ,  EVANS, Joseph, T.

Inventor： EVANS, Joseph, T.

IPC: G11C5/14 ,  G11C16/30

CPC classification number: G11C5/148 ,  G11C7/1006 ,  G11C7/20 ,  G11C7/24 ,  G11C8/20 ,  G11C11/221 ,  G11C14/00 ,  G11C16/22 ,  G11C19/005 ,  H01L27/11502 ,  H03K3/356008

Abstract: A circuit having an autonomous ferroelectric memory latch (AML) is disclosed. An AML characterized by an AML input, an AML output, a first AML power contact, a second AML power contact and an AML state, and a first switch in series with one of the AML input or the AML output. The switch is positioned to prevent the state of the AML from changing when power is provided between the first and second AML power contacts, In one aspect of the invention, the circuit could include a second switch in series with the other of the AML input or the AML output and a latch in series with the AML input or the AML output. The latch is positioned such that a direct path back does not exist between the AML output and the AML input.

Abstract translation: 公开了具有自主铁电存储器锁存器（AML）的电路。 AML以AML输入，AML输出，第一AML电源触点，第二AML电源触点和AML状态为特征，以及与AML输入或AML输出之一串联的第一开关。 当在第一和第二AML电力触点之间提供电力时，开关被定位成防止AML的状态改变。在本发明的一个方面，该电路可以包括与另一个AML输入串联的第二开关， AML输出和与AML输入或AML输出串联的锁存器。 锁存器的定位使得AML输出和AML输入之间不存在直接回路。

公开(公告)号：WO2012074776A2

公开(公告)日：2012-06-07

申请号：PCT/US2011/061266

申请日：2011-11-17

Applicant: RADIANT TECHNOLOGIES, INC. ,  EVANS, Joseph, T. ,  WARD, Calvin, B.

Inventor： EVANS, Joseph, T. ,  WARD, Calvin, B.

IPC: G11C11/22

CPC classification number: G11C11/221 ,  G11C11/2259 ,  G11C11/2273 ,  G11C11/2275 ,  G11C11/2293 ,  G11C11/5657 ,  G11C27/005

Abstract: A ferroelectric memory having a plurality of ferroelectric memory cells, each ferroelectric memory cell including a ferroelectric capacitor is disclosed. The ferroelectric memory includes read and write lines and a plurality of ferroelectric memory cell select buses, one select bus corresponding to each of the ferroelectric memory cells. Each of the ferroelectric memory cells includes first and second gates for connecting the ferroelectric memory cell to the read line and the write line, respectively, in response to signals on the ferroelectric memory cell select bus corresponding to that ferroelectric memory cell. A write circuit causes a charge to be stored in the ferroelectric capacitor of the ferroelectric memory cell currently connected to the write line, the charge having a value determined by a data value having at least three states. A read circuit measures the charge stored in the ferroelectric capacitor of the ferroelectric memory cell currently connected to the read line to generate an output value, the output value corresponding to one of the states.

Abstract translation: 公开了具有多个铁电存储单元的铁电存储器，每个强电介质存储单元包括铁电电容器。 铁电存储器包括读写线和多个铁电存储器单元选择总线，每个铁电存储单元相应的一个选择总线。 每个铁电存储单元包括用于响应于与该铁电存储单元相对应的强电介质存储单元选择总线上的信号而分别将铁电存储单元连接到读取线和写入线的第一和第二栅极。 写入电路使得电荷存储在当前连接到写入线的铁电存储单元的铁电电容器中，电荷具有由具有至少三个状态的数据值确定的值。 读取电路测量存储在当前连接到读取线的铁电存储器单元的铁电电容器中的电荷，以产生与其中一个状态对应的输出值。