公开(公告)号：WO2017040053A1

公开(公告)日：2017-03-09

申请号：PCT/US2016/047584

申请日：2016-08-18

Applicant: MICRON TECHNOLOGY, INC.

Inventor： NICHOLES, Steven C. ,  CHAVAN, Ashonita A. ,  ROCKLEIN, Matthew N.

IPC: G11C11/22 ,  H01L27/115

CPC classification number: G11C11/225 ,  G11C11/22 ,  G11C11/221 ,  G11C11/2273 ,  G11C11/2275 ,  G11C11/2297 ,  G11C11/5657 ,  G11C13/047 ,  G11C14/00 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/56 ,  H01L28/65 ,  H01L28/75

Abstract: Methods of operating a ferroelectric memory cell. The method comprises applying one of a positive bias voltage and a negative bias voltage to a ferroelectric memory cell comprising a capacitor including a top electrode, a bottom electrode, a ferroelectric material between the top electrode and the bottom electrode, and an interfacial material between the ferroelectric material and one of the top electrode and the bottom electrode. The method further comprises applying another of the positive bias voltage and the negative bias voltage to the ferroelectric memory cell to switch a polarization of the ferroelectric memory cell, wherein an absolute value of the negative bias voltage is different from an absolute value of the positive bias voltage. Ferroelectric memory cells are also described.

Abstract translation: 操作铁电存储单元的方法。 该方法包括将正偏置电压和负偏置电压中的一个施加到包括上电极，底电极，顶电极和底电极之间的铁电材料的电容器和铁电存储单元之间的界面材料的铁电存储单元， 铁电材料和顶电极和底电极之一。 该方法还包括将另一个正偏置电压和负偏置电压施加到铁电存储单元以切换铁电存储单元的极化，其中负偏置电压的绝对值与正偏压的绝对值不同 电压。 还描述了铁电存储器单元。

公开(公告)号：WO2016155368A1

公开(公告)日：2016-10-06

申请号：PCT/CN2015/098219

申请日：2015-12-22

Applicant: 山东华芯半导体有限公司

Inventor： 韩小炜

IPC: G11C14/00

CPC classification number: G11C14/00

Abstract: 一种基于RRAM单元的非易失性SRAM存储单元，包括一个传统的六晶体管SRAM单元6T-SRAM和两个1T1R RRAM单元；其中，6T-SRAM包括：两个N型晶体管（NAL，NAR），分别连接同侧的数据线（Q，QB）和位线（BL，BLB）；四个晶体管（PL，NL，PR，NR）组成两个交叉耦合的反相器，输出分别是第一数据线（Q）和第二数据线（QB）；两个RRAM单元都分别包括一个阻变电阻（RL，RR）和一个晶体管（RNSL，RNSR），阻变电阻（RL，RR）的阴极连接至同侧的数据线（Q，QB），阻变电阻（RL，RR）的阳极连接至晶体管（RNSL，RNSR）的源极，晶体管（RNSL，RNSR）的漏极连接至相对侧的位线（BLB，BL），晶体管（RNSL，RNSR）的栅极连接至电阻字线（RWL）。该存储单元能够实现数据自动恢复、下电情况下仍可保持存储数据、存储器待机模式功耗低、操作方便等优点。

公开(公告)号：WO2015116107A1

公开(公告)日：2015-08-06

申请号：PCT/US2014/013885

申请日：2014-01-30

Applicant: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P.

Inventor： JEON, Yoocharn ,  FOLTIN, Martin

IPC: G11C11/407 ,  G11C5/14

CPC classification number: G11C13/0069 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0033 ,  G11C13/0035 ,  G11C13/004 ,  G11C13/0097 ,  G11C14/00

Abstract: A memristor memory is disclosed. In an example, a method of controlling a memristor memory includes operating the memristor memory in a volatile mode, wherein switching a state of a memristor cell is with a low writing load. The method also includes operating the same memristor memory in a non-volatile mode, wherein switching a state of the memristor cell is with a high writing load.

Abstract translation: 忆阻记忆体被公开。 在一个示例中，控制忆阻存储器的方法包括以易失性模式操作忆阻器存储器，其中，忆阻单元的状态切换具有低写入负载。 该方法还包括在非易失性模式下操作相同的忆阻器存储器，其中开关忆阻器单元的状态具有高写入负载。

公开(公告)号：WO2011011007A1

公开(公告)日：2011-01-27

申请号：PCT/US2009/051564

申请日：2009-07-23

Applicant: HEWLETT-PACKARD DEVELOPMENT, COMPANY, L.P. ,  SNIDER, Gregory Stuart

Inventor： SNIDER, Gregory Stuart

IPC: G11C11/41 ,  G11C11/413 ,  G11C11/4193 ,  G11C5/14

CPC classification number: G11C13/0069 ,  G11C5/141 ,  G11C13/0007 ,  G11C14/00 ,  G11C19/00 ,  H03K3/45

Abstract: One embodiments of the present invention is directed to a single-bit memory cell comprising a transistor-based bit latch having a data state and a memristor, coupled to the transistor-based bit latch, in which the data state of the transistor-based bit latch is stored by a store operation and from which a previously-stored data state is retrieved and restored into the transistor-based bit latch by a restore operation. Another embodiment of the present invention is directed to a single-bit memory cell comprising a master-slave flip flop and a slave flip flop, and a power input, a memristor, a memory-cell power input, a first memory-cell clock input, a second memory-cell clock input, a memory-cell data input, a memory-cell data output, and two or more memory-cell control inputs.

Abstract translation: 本发明的一个实施例涉及一种单位存储单元，其包括耦合到基于晶体管的位锁存器的具有数据状态的晶体管基锁存器和忆阻器，其中基于晶体管的位的数据状态 通过存储操作存储锁存器，并且通过恢复操作从存储操作中检索先前存储的数据状态并将其恢复到基于晶体管的位锁存器中。 本发明的另一实施例涉及一种包括主从触发器和从触发器的单位存储单元，以及电源输入，忆阻器，存储单元电源输入，第一存储单元时钟输入 ，第二存储单元时钟输入，存储单元数据输入，存储单元数据输出以及两个或多个存储单元控制输入。

公开(公告)号：WO2009019273A1

公开(公告)日：2009-02-12

申请号：PCT/EP2008/060282

申请日：2008-08-05

Applicant: DOLPHIN INTEGRATION ,  ZANGARA, Louis ,  LEROY, Fabien

Inventor： ZANGARA, Louis ,  LEROY, Fabien

IPC: G11C11/00 ,  G11C7/20 ,  G11C7/18

CPC classification number: G11C11/419 ,  G11C7/1006 ,  G11C14/00 ,  G11C15/04

Abstract: The invention concerns a memory having an array of memory cells (1002) arranged in rows and columns, each being capable of storing at least one first bit of data and comprising an output arranged to output said at least one first bit of data; a plurality of groups of bit lines (1004), each group of bit lines being associated with one of said rows or columns of memory cells, the output of each memory cell being connected to at least one bit line of a group of bit lines, said connection indicating at least one second bit of data, said second bit of data being non-volatile; and output circuitry (1006) coupled to said groups of bit lines and comprising detection circuitry arranged to determine said first and second bits, and logic circuitry arranged to perform a logic function on said first and second bits.

Abstract translation: 本发明涉及具有以行和列排列的存储单元阵列（1002）的存储器，每个存储器单元能够存储至少一个第一数据位，并且包括被输出以输出所述至少一个第一数据位的输出; 多个位线组（1004），每组位线与存储器单元的所述行或列之一相关联，每个存储单元的输出连接到一组位线的至少一个位线， 所述连接指示至少一个第二位数据，所述第二位数据是非易失性的; 以及耦合到所述位线组的输出电路（1006），并且包括布置成确定所述第一和第二位的检测电路以及布置成在所述第一和第二位上执行逻辑功能的逻辑电路。

公开(公告)号：WO2006137876A3

公开(公告)日：2007-05-31

申请号：PCT/US2005033718

申请日：2005-09-20

Applicant: NANTERO INC ,  BERTIN CLAUDE L ,  RUECKES THOMAS ,  SEGAL BRENT M

Inventor： BERTIN CLAUDE L ,  RUECKES THOMAS ,  SEGAL BRENT M

IPC: G01B11/26 ,  G01C1/00

CPC classification number: G11C13/025 ,  B82Y10/00 ,  B82Y30/00 ,  G11C14/00 ,  G11C23/00 ,  H01H1/0094

Abstract: Random access memory including nanotube switching elements. A memory cell includes first and second nanotube switching elements and an electronic memory. Each nanotube switching element includes an output node, a nanotube channel element having at least one electrically conductive nanotube, and a control structure having a set electrode and a release electrode disposed in relation to the nanotube channel element to controllably form and unform an electrically conductive channel between said channel electrode and said output node. The electronic memory has cross-coupled first and second inverters. The input node of the first inverter is coupled to the set electrode of the first nanotube switching element and to the output node of the second nanotube switching element. The input node of the of the second inverter is coupled to the set electrode of the second nanotube switching element and to the output node of the first nanotube switching element; and the channel electrode is coupled to a channel voltage line. The release electrode of the first nanotube switching element is coupled to the release electrode of the second nanotube switching element and wherein both release electrodes are coupled to a release line. The cell can operate as a normal electronic memory, or can operate in a shadow memory or store mode (e.g., when power is interrupted) to transfer the electronic memory state to the nanotube switching elements. The device may later be operated in a recall mode where the state of the nanotube switching elements may be transferred to the electronic memory.

Abstract translation: 随机存取存储器包括纳米管开关元件。 存储单元包括第一和第二纳米管切换元件和电子存储器。 每个纳米管开关元件包括输出节点，具有至少一个导电纳米管的纳米管通道元件和具有相对于纳米管通道元件设置的设定电极和释放电极的控制结构，以可控地形成和取消导电通道 在所述通道电极和所述输出节点之间。 电子存储器具有交叉耦合的第一和第二逆变器。 第一反相器的输入节点耦合到第一纳米管开关元件的设定电极和第二纳米管开关元件的输出节点。 第二反相器的输入节点耦合到第二纳米管开关元件的设定电极和第一纳米管开关元件的输出节点; 并且沟道电极耦合到沟道电压线。 第一纳米管开关元件的释放电极耦合到第二纳米管开关元件的释放电极，并且其中两个释放电极耦合到释放线。 电池可以作为普通电子存储器工作，或者可以在阴影存储器或存储模式（例如，当电力中断时）操作以将电子存储器状态传送到纳米管开关元件。 该装置可以稍后在调谐模式下操作，其中纳米管切换元件的状态可以被传送到电子存储器。

公开(公告)号：WO2006036907A2

公开(公告)日：2006-04-06

申请号：PCT/US2005/034468

申请日：2005-09-23

Applicant: CYPRESS SEMICONDUCTOR CORPORATION ,  TAHERI, Babak, A. ,  MAHESHWARI, Sanjeev

Inventor： TAHERI, Babak, A. ,  MAHESHWARI, Sanjeev

IPC: G11C11/34

CPC classification number: G11C17/146 ,  G11C14/00 ,  G11C17/16

Abstract: A one-time programmable (OTP) latch circuit can include a single OTP device capable of storing a logic value in a nonvolatile fashion, or only two OTP devices in the event redundancy is desired. A latch section can latch a data value based on a comparison between a current drawn according to the one OTP device, and a reference current generated without and OTP device. An OTP device can include a gate oxide antifuse (GOAF) device.

Abstract translation: 一次性可编程（OTP）锁存电路可以包括能够以非易失性方式存储逻辑值的单个OTP设备，或者在需要冗余的情况下仅包括两个OTP设备。 基于根据一个OTP设备绘制的电流与不使用OTP设备的参考电流进行比较，锁存部分可以锁存数据值。 OTP设备可以包括栅极氧化物反熔丝（GOAF）器件。

公开(公告)号：WO2005098867A3

公开(公告)日：2005-12-22

申请号：PCT/US2005010432

申请日：2005-03-29

Applicant: IMPINJ INC ,  DIORIO CHRISTOPHER J ,  BERNARD FREDERIC J ,  HUMES TODD E ,  PESAVENTO ALBERTO

Inventor： DIORIO CHRISTOPHER J ,  BERNARD FREDERIC J ,  HUMES TODD E ,  PESAVENTO ALBERTO

IPC: G11C7/20 ,  G11C14/00 ,  G11C16/04 ,  G11C17/12 ,  H01L29/788

CPC classification number: G11C16/0441 ,  G11C7/20 ,  G11C14/00 ,  G11C16/045

Abstract: Rewriteable electronic fuses (30) include latches (32) and/or logic gates (32) coupled to one or more nonvolatile memory elements (34). The nonvolatile memory elements are configured to be programmed to memory values capable of causing associated electronic circuits to settle to predetermined states as power-up or reset signals are applied to the fuses. Although not required, the nonvolatile memory elements used in the rewriteable electronic fuses may comprise floating-gate transistors (48, 50). An amount of charge stored on the floating-gate of a given floating-gate transistor determines the memory value and, consequently, the state to which a fuse settles upon power-up or reset of the fuse.

Abstract translation: 可重写电子熔丝（30）包括耦合到一个或多个非易失性存储元件（34）的锁存器（32）和/或逻辑门（32）。 非易失性存储器元件被配置为被编程为能够使相关联的电子电路稳定到预定状态的存储器值，因为上电或复位信号被施加到保险丝。 虽然不是必需的，但是在可重写电子熔丝中使用的非易失性存储元件可以包括浮栅晶体管（48,50）。 存储在给定浮栅晶体管的浮置栅极上的电荷量确定存储器值，并且因此确定保险丝上电或复位时保险丝熔断的状态。

公开(公告)号：WO2004086512A1

公开(公告)日：2004-10-07

申请号：PCT/JP2003/003682

申请日：2003-03-26

Applicant: 富士通株式会社 ,  佐藤 綾子

Inventor： 佐藤 綾子

IPC: H01L29/788

CPC classification number: G11C16/0466 ,  G11C14/00 ,  G11C14/0063

Abstract: 　窒化膜内のトラップ領域に電荷を蓄積して記憶状態を保持する不揮発性半導体記憶回路ＭＴ１、ＭＴ２の出力ノードと、その出力をラッチする揮発性記憶回路１０の内部ノードＮ１、Ｎ２とを接続することで、動作速度が速いとともに１記憶単位のサイズが小さく、電源が供給されなくともデータを消失せずにデータを保持する不揮発なデータ保持機能を実現することができるようにする。

Abstract translation: 可以通过连接非易失性半导体存储器电路MT1和MT2的输出节点来实现半导体存储器，该半导体存储器在增加操作速度的同时减小单元存储器大小并且即使不提供电力来保持数据的非易失性数据保持功能也可以实现 通过存储在氮化物膜的陷阱区域中的存储器状态与用于锁存非易失性半导体存储器电路MT1和MT2的输出的易失性存储器电路（10）的内部节点N1和N2充电。

公开(公告)号：WO2004072335A2

公开(公告)日：2004-08-26

申请号：PCT/US2004004107

申请日：2004-02-12

Applicant: NANTERO INC ,  JAIPRAKASH VENKATACHALAM C ,  WARD JONATHAN W ,  RUECKES THOMAS ,  SEGAL BRENT M

Inventor： JAIPRAKASH VENKATACHALAM C ,  WARD JONATHAN W ,  RUECKES THOMAS ,  SEGAL BRENT M

IPC: B81B3/00 ,  G11C13/02 ,  G11C23/00 ,  H01H59/00 ,  D01F

CPC classification number: G11C23/00 ,  B81B2201/016 ,  B81B2203/0127 ,  B81C1/00142 ,  B81C2201/0109 ,  B82Y10/00 ,  G11C13/025 ,  G11C14/00 ,  G11C2213/16 ,  G11C2213/77 ,  G11C2213/81 ,  H01H1/0094

Abstract: Electro-mechanical switches and memory cells using vertically-disposed nanofabric articles and methods of making the same are described. An electro-mechanical device, includes a structure having a major horizontal surface and a channel formed therein. A conductive trace is in the channel; and a nanotube article vertically suspended in the channel, in spaced relation to a vertical wall of the channel. The article is electro-mechanically deflectable in a horizontal direction toward the conductive trace. Under certain embodiments, the vertically suspended extent of the nanotube article is defined by a thin film process. Under certain embodiments, the vertically suspended extent of the nanotube article is about 50 nanometers or less. Under certain embodiments, the nanotube article is clamped with a conducting material disposed in porous spaces between some nanotubes of the nanotube article. Under certain embodiments, the nanotube article is formed from a porous nanofabric. Under certain embodiments, the nanotube article is electromechanically deflectable into contact with the conductive trace and the contact is either a volatile state or non-volatile state depending on the device construction. Under certain embodiments, the vertically oriented device is arranged into various forms of three-trace devices. Under certain embodiments, the channel may be used for multiple independent devices, or for devices that share a common electrode.

Abstract translation: 描述了使用垂直布置的纳米制品的机电开关和存储单元及其制造方法。 机电装置包括具有主要水平表面和形成在其中的通道的结构。 通道中有导电迹线; 以及垂直悬挂在所述通道中的与所述通道的垂直壁成间隔开的纳米管制品。 该物品在水平方向上可电导向导电迹线偏转。 在某些实施方案中，纳米管制品的垂直悬浮程度由薄膜工艺限定。 在某些实施方案中，纳米管制品的垂直悬浮程度为约50纳米或更小。 在某些实施例中，纳米管制品被夹持在布置在纳米管制品的一些纳米管之间的多孔空间中的导电材料上。 在某些实施方案中，纳米管制品由多孔纳米纤维形成。 在某些实施例中，取决于器件结构，纳米管制品在机电上可偏转成与导电迹线接触，并且触点是易失性状态或非易失性状态。 在某些实施例中，垂直取向的装置被布置成各种形式的三轨迹装置。 在某些实施例中，信道可以用于多个独立设备，或用于共享公共电极的设备。