公开(公告)号：WO2007047390A3

公开(公告)日：2007-06-14

申请号：PCT/US2006039931

申请日：2006-10-10

Applicant: SANDISK CORP ,  PHAM TUAN D ,  HIGASHITANI MASAAKI

Inventor： PHAM TUAN D ,  HIGASHITANI MASAAKI

IPC: H01L21/762 ,  H01L21/311 ,  H01L21/8239 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115

CPC classification number: H01L27/11526 ,  H01L21/31111 ,  H01L21/3212 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11531

Abstract: A non-volatile memory is formed having shallow trench isolation structures between floating gates and having control gates extending between floating gates where shallow trench isolation dielectric is etched. Control of etch depth is achieved using ion implantation to create a layer of dielectric with a high etch rate compared with the underlying dielectric. A conductive layer overlies the substrate during implantation. A substrate having small polysilicon features in a memory array and large polysilicon features in a peripheral area is accurately planarized using protrusions in the peripheral area and a soft chemical mechanical polishing step that stops when protrusions are removed.

Abstract translation: 形成在浮动栅极之间具有浅沟槽隔离结构并且具有在浮动栅极之间延伸的控制栅极的非易失性存储器，其中浅沟槽隔离电介质被蚀刻。 使用离子注入实现蚀刻深度的控制，以与下层电介质相比形成具有高蚀刻速率的电介质层。 在植入期间，导电层覆盖衬底。 存储器阵列中具有小的多晶硅特征的基板和外围区域中的大多晶硅特征使用周边区域中的突起精细地平坦化，并且当突起被去除时停止的软化学机械抛光步骤。