公开(公告)号：WO2017190123A1

公开(公告)日：2017-11-02

申请号：PCT/US2017/030359

申请日：2017-05-01

Applicant: TEXAS INSTRUMENTS INCORPORATED ,  TEXAS INSTRUMENTS JAPAN LIMITED

Inventor： NARAYANAN, Prakash ,  MITTAL, Rajesh ,  MEHROTRA, Rajat

IPC: G01R31/303

CPC classification number: G01R31/31713 ,  G01R31/3177 ,  G01R31/318536 ,  G01R31/318572

Abstract: In described examples, an integrated circuit (200) includes functional circuitry (214) and testing circuitry (212). A set of pads (P 0 -P 4 ) is operable in a first state for communicating testing signals to the testing circuitry (212) and operable in a second state for communicating input/output signals to the functional circuitry (214). A second set of pads (P 5 -P 9 ), differing from the set of pads (P 0 -P 4 ), is operable in the second state for communicating testing signals to the testing circuitry (212) for testing signals associated in the second state with the set of pads (P 0 -P 4 ).

Abstract translation: 在所描述的示例中，集成电路（200）包括功能电路（214）和测试电路（212）。 一组焊盘（P 0 -P 4）可在第一状态下工作，用于将测试信号传送给测试电路（212）并可在第二状态下工作以进行通信 输入/输出信号到功能电路（214）。 第二组焊盘（P 5 -P 9）不同于该组焊盘（P 0 -P 4） ）可操作于第二状态，用于将测试信号传送到测试电路（212），用于测试与第二状态相关联的信号，其中该组焊盘（P 0 -P _{4 ）。}

公开(公告)号：WO2017190124A1

公开(公告)日：2017-11-02

申请号：PCT/US2017/030360

申请日：2017-05-01

Applicant: TEXAS INSTRUMENTS INCORPORATED ,  TEXAS INSTRUMENTS JAPAN LIMITED

Inventor： KAWOOSA, Mudasir, Shafat ,  MITTAL, Rajesh

IPC: G06F11/267 ,  G01R31/3185

CPC classification number: G01R31/3177 ,  G01R31/31701 ,  G01R31/3172 ,  G01R31/31723 ,  G01R31/318572 ,  G01R31/31926

Abstract: In described examples, an integrated circuit (100) includes functional circuitry (114) and testing circuitry (112). The testing circuitry (112) has a state machine operable in multiple different states. The integrated circuit (100) also has a pin (P2) for receiving a signal (TMS). The state machine is operable to transition between states in response to a change in level of the signal (TMS). Circuitry couples the signal (TMS) of the pin (P2), in a first level, to the state machine in a first time period for causing the state machine to enter a predetermined state, and circuitry (124) maintains the signal (TMS) in the first level to the state machine in a second time period for maintaining the state machine in the predetermined state. Also, during the second time period, circuitry couples data received at the pin (P2) to a destination circuit (122) other than the state machine. The destination circuit (122) is operable to perform successive scan tests using data from the pin (P2) without a power on reset of the functional circuitry (114).

Abstract translation: 在所描述的示例中，集成电路（100）包括功能电路（114）和测试电路（112）。 测试电路（112）具有可在多种不同状态下操作的状态机。 集成电路（100）还具有用于接收信号（TMS）的引脚（P2）。 状态机可操作以响应于信号的电平（TMS）的变化而在状态之间转换。 电路在第一时间段将引脚（P2）的信号（TMS）在第一时间段内耦合到状态机，以使状态机进入预定状态，并且电路（124）维持信号（TMS） 在状态机的第一级中在第二时间段内保持状态机处于预定状态。 而且，在第二时间段期间，电路将在引脚（P2）处接收的数据耦合到除状态机之外的目的地电路（122）。 目的地电路（122）可操作以使用来自引脚（P2）的数据在不对功能电路（114）进行加电复位的情况下执行连续的扫描测试。

公开(公告)号：WO2015172086A1

公开(公告)日：2015-11-12

申请号：PCT/US2015/029996

申请日：2015-05-08

Applicant: TEXAS INSTRUMENTS INCORPORATED ,  TEXAS INSTRUMENTS JAPAN LIMITED

Inventor： POTTY, Sreenath Narayanan ,  MITTAL, Rajesh ,  KAWOOSA, Mudasir Shafat ,  SINGHAL, Vivek

IPC: G01R31/3177 ,  G06F11/25

CPC classification number: G01R31/3177 ,  G01R31/3172 ,  G01R31/31723 ,  G01R31/31727 ,  G01R31/3183 ,  G01R31/318335 ,  G01R31/318533 ,  G01R31/318544 ,  G01R31/318563

Abstract: In described examples of a circuit (100) for testing an integrated circuit (IC), the circuit (100) includes an input converter (104) that receives N scan inputs (102) and generates M pseudo scan inputs (106), where M and N are integers. A scan compression architecture (110) is coupled to the input converter (104) and generates P pseudo scan outputs (116) in response to the M pseudo scan inputs (106). An output converter (118) is coupled to the scan compression architecture (110) and generates Q scan outputs (120) in response to the P pseudo scan outputs (116), where P and Q are integers. The input converter (104) receives the N scan inputs (102) at a first frequency and generates the M pseudo scan inputs (106) at a second frequency. The output converter (118) receives the P pseudo scan outputs (116) at the second frequency and generates the Q scan outputs (120) at the first frequency.

Abstract translation: 在用于测试集成电路（IC）的电路（100）的所述示例中，电路（100）包括接收N个扫描输入（102）并产生M个伪扫描输入（106）的输入转换器（104），其中M 和N是整数。 扫描压缩架构（110）耦合到输入转换器（104），并且响应于M个伪扫描输入（106）产生P伪扫描输出（116）。 输出转换器（118）耦合到扫描压缩架构（110）并响应于P伪扫描输出（116）产生Q扫描输出（120），其中P和Q是整数。 输入转换器（104）以第一频率接收N个扫描输入（102），并以第二频率产生M个伪扫描输入（106）。 输出转换器（118）以第二频率接收P伪扫描输出（116），并以第一频率产生Q扫描输出（120）。

公开(公告)号：WO2013173192A1

公开(公告)日：2013-11-21

申请号：PCT/US2013/040609

申请日：2013-05-10

Applicant: TEXAS INSTRUMENTS INCORPORATED ,  TEXAS INSTRUMENTS JAPAN LIMITED

Inventor： MITTAL, Rajesh ,  SABBARWAL, Puneet ,  NARAYANAN, Prakash ,  PAREKHJI, Rubin, Ajit

IPC: G01R31/26 ,  G01R31/3183

CPC classification number: G01R31/318555 ,  G01R31/3177 ,  G01R31/3183 ,  G01R31/318533 ,  G01R31/318536 ,  G01R31/318544 ,  G01R31/318569 ,  G01R31/318594

Abstract: Various embodiments of methods and integrated circuits capable of generating a test mode control signal for a scan test through a scan chain (such as in an integrated circuit) are provided. The integrated circuit includes a test pattern detection block (202), a counter circuit (204), and a control circuit (206). The test pattern detection block is configured to receive a detection pattern (208) and to detect a first pattern corresponding to a shift phase and a second pattern corresponding to a capture phase of a test pattern based on the detection pattern and to generate a trigger signal based upon the detection of the patterns. The control circuit generates and controls the test mode control signal based on the count states. The counter circuit is configured to generate one or more count states corresponding to one of the shift phase, the capture phase and the clock signal (209) based on the detected pattern.

Abstract translation: 提供了能够通过扫描链（例如集成电路）产生用于扫描测试的测试模式控制信号的方法和集成电路的各种实施例。 集成电路包括测试图案检测块（202），计数器电路（204）和控制电路（206）。 测试图案检测块被配置为接收检测图案（208）并且基于检测图案检测对应于移位相位和对应于测试图案的捕获相位的第二图案的第一图案并产生触发信号 基于模式的检测。 控制电路根据计数状态生成并控制测试模式控制信号。 计数器电路被配置为基于检测到的模式产生与移位相位，捕获相位和时钟信号（209）中的一个对应的一个或多个计数状态。