中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

19 records (took 0.015 seconds)

    MEMRISTIVE NEURAL NETWORK COMPUTING ENGINE USING CMOS-COMPATIBLE CHARGE-TRAP-TRANSISTOR (CTT)
    1.
    发明申请
    MEMRISTIVE NEURAL NETWORK COMPUTING ENGINE USING CMOS-COMPATIBLE CHARGE-TRAP-TRANSISTOR (CTT) 审中-公开

    公开(公告)号：WO2019100036A1

    公开(公告)日：2019-05-23

    申请号：PCT/US2018/061893

    申请日：2018-11-19

    Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA

    Inventor： CHANG, Mau-Chung Frank ,  DU, Yuan ,  DU, Li

    IPC: G06N3/04 ,  G06N3/02 ,  G06N3/08

    CPC classification number: G06N3/0635

    Abstract: A neural network computing engine having an array of charge-trap-transistor (CTT) elements which are utilized as analog multipliers with all weight values preprogrammed into each CTT element as a CTT threshold voltage, with multiplicator values received from the neural network inference mode. The CTT elements perform computations of a fully connected (FC) neural network with each CTT element representing a neuron. Row resistors for each row of CTT element sum output currents as partial summation results. Counted pulse generators write weight values under control of a pulse generator controller. A sequential analog fabric (SAF) feeds multiple drain voltages in parallel to the CTT array to enable parallel analog computations of neurons. Partial summation results are read by an analog-to-digital converter (ADC).

    RESONANT TYPES OF COMMON-SOURCE/COMMON-EMITTER STRUCTURE FOR HIGH GAIN AMPLIFICATION
    2.
    发明申请
    RESONANT TYPES OF COMMON-SOURCE/COMMON-EMITTER STRUCTURE FOR HIGH GAIN AMPLIFICATION 审中-公开
    公共源/共同发射体结构的高增益型共振型

    公开(公告)号：WO2007019147A2

    公开(公告)日：2007-02-15

    申请号：PCT/US2006/029970

    申请日：2006-07-31

    Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ,  CHANG, Mau-Chung Frank ,  HUANG, Daquan

    Inventor： CHANG, Mau-Chung Frank ,  HUANG, Daquan

    IPC: H03M1/66

    CPC classification number: H03F3/193 ,  H03F3/2176

    Abstract: Radio frequency/millimeter wave integrated circuits (RF/MMICs) that employ a resonance mechanism between an input stage and a transistor are disclosed. The circuits contain an input stage, a transistor; and a transformer connected between either a gate or a base of the transistor and a voltage supply of the input stage. The methods disclosed maximize either a collector current or a drain current of a transistor by placing a transformer between the transistor and a voltage source.

    Abstract translation: 公开了在输入级和晶体管之间采用共振机构的射频/毫米波集成电路（RF / MMIC）。 电路包含输入级，晶体管; 以及连接在晶体管的栅极或基极与输入级的电压源之间的变压器。 所公开的方法通过在晶体管和电压源之间放置变压器来最大化晶体管的集电极电流或漏极电流。

    SELF TRACK SCHEME FOR MULTI FREQUENCY BAND SERIALIZER DE-SERIALIZER I/O CIRCUITS
    4.
    发明申请
    SELF TRACK SCHEME FOR MULTI FREQUENCY BAND SERIALIZER DE-SERIALIZER I/O CIRCUITS 审中-公开
    多频段串行编解码器I / O电路的自拍方案

    公开(公告)号：WO2014074301A1

    公开(公告)日：2014-05-15

    申请号：PCT/US2013/066194

    申请日：2013-10-22

    Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA

    Inventor： LEE, Sheau Jiung ,  CHANG, Mau-Chung Frank ,  KIM, Yanghyo

    IPC: G06F13/00 ,  G06F13/38

    CPC classification number: H04L27/38 ,  G06F5/16 ,  G06F13/4059 ,  G06F13/4072 ,  G06F13/4278 ,  H04L27/364

    Abstract: A serializer and de-serializer circuit having self tracking circuitry which is particularly well-suited for use in communicating digital data from one integrated circuit (chip) to another for implementing chip-to-chip communications is presented. The circuits are scalable and utilize a multi-frequency modulation mechanism (e.g., QAM) for converting digital data bits into a serial analog stream at multiple frequencies for communication over a chip I/O connection. The track pulse generated on the transmitter side is serialized through the same path as the data, and demodulated through the same path in the de-serializer to provide synchronization with the data, without the need for complicated base band processing.

    Abstract translation: 具有自我跟踪电路的串行器和解串器电路，其特别适用于将数字数据从一个集成电路（芯片）传送到另一个集成电路（芯片）以实现芯片到芯片通信。 这些电路是可扩展的并且利用多频调制机制（例如，QAM），用于将数字数据位转换成多个频率的串行模拟流，用于通过芯片I / O连接进行通信。 在发射机侧产生的跟踪脉冲通过与数据相同的路径进行串行化，并通过解串器中相同的路径解调，以提供与数据的同步，而不需要复杂的基带处理。

    FREQUENCY TRANSLATING BACKSCATTER MODULATOR WITH ENVELOPE CONTROL TO SUPPORT OFDM/QAM AND OTHER ENVELOPE MODULATED WIRELESS PROTOCOLS
    7.
    发明申请
    FREQUENCY TRANSLATING BACKSCATTER MODULATOR WITH ENVELOPE CONTROL TO SUPPORT OFDM/QAM AND OTHER ENVELOPE MODULATED WIRELESS PROTOCOLS 审中-公开
    带信封控制的频率转换后向散射调制器支持OFDM / QAM和其他包络调制无线协议

    公开(公告)号：WO2017222661A2

    公开(公告)日：2017-12-28

    申请号：PCT/US2017/031782

    申请日：2017-05-09

    Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA ,  CALIFORNIA INSTITUTE OF TECHNOLOGY

    Inventor： CHANG, Mau-Chung Frank ,  TANG, Adrian J.

    Abstract: A backscatter modulator for providing low power wireless communications. The disclosed modulator provides phase control for discriminating backscatter from the antenna versus other objects. In addition, the disclosed backscatter modulator provides amplitude modulation so that the technique can provide a non-constant envelope which can provide an intentional imbalance to manipulate super-position to provide envelope control of the reflected signal, while still maintaining the frequency translation properties. The disclosed backscatter modulator thus allows compatibility with QAM, OFDM and other non-constant envelope modulation schemes to be backscattered, while still supporting the frequency translation behavior.

    Abstract translation:

    用于提供低功率无线通信的反向散射调制器。 所公开的调制器提供用于区分来自天线的反向散射与其他物体的相位控制。 另外，所公开的背向散射调制器提供幅度调制，使得该技术可以提供非恒定包络，该包络可以提供有意不平衡以操纵超级位置以提供对反射信号的包络控制，同时仍保持频率变换特性。 所公开的反向散射调制器因此允许与QAM，OFDM和其他非恒定包络调制方案的兼容性被反向散射，同时仍支持频率转换行为。

    DIFFERENTIAL CURRENT MODE LOW LATENCY MODULATION AND DEMODULATION FOR CHIP-TO-CHIP CONNECTION
    8.
    发明申请
    DIFFERENTIAL CURRENT MODE LOW LATENCY MODULATION AND DEMODULATION FOR CHIP-TO-CHIP CONNECTION 审中-公开
    差分电流模式低切换调制和芯片间切换连接的解调

    公开(公告)号：WO2014182474A1

    公开(公告)日：2014-11-13

    申请号：PCT/US2014/035533

    申请日：2014-04-25

    Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA

    Inventor： LEE, Sheau Jiung ,  CHANG, Mau-Chung Frank ,  CHO, Wei-Han ,  KIM, Yanghyo

    IPC: H03M3/00

    CPC classification number: H04L27/362 ,  H04L5/06 ,  H04L25/0282 ,  H04L25/0294 ,  H04L27/38

    Abstract: A chip-to-chip communications circuit which is particularly well-suited for short range communication (less than a few inches) from one integrated circuit (chip) to another is presented. The circuits preferably utilize multi-frequency quadrature amplitude modulation (QAM) mechanisms for converting digital data bits from a parallel form into a serial analog stream for communication over a chip I/O connection. Differential current mode modulation in the transmitter, and demodulation in the receiver, are utilized which reduce latency and power-consumption while increasing manufacturing yields and resilience to process variations.

    Abstract translation: 提出了一种特别适用于从一个集成电路（芯片）到另一个集成电路（芯片）的短距离通信（小于几英寸）的芯片到芯片通信电路。 这些电路优选地利用用于将数字数据位从并行形式转换成用于通过芯片I / O连接进行通信的串行模拟流的多频正交幅度调制（QAM）机制。 利用发射机中的差分电流模式调制和接收机中的解调，这降低了延迟和功耗，同时提高了制造成本和对工艺变化的弹性。

Patent Agency Ranking