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公开(公告)号:WO2019067836A1
公开(公告)日:2019-04-04
申请号:PCT/US2018/053304
申请日:2018-09-28
Applicant: VERSUM MATERIALS US, LLC
Inventor: GE, Jhih, Kuei , LEE, Yi-Chia , LIU, Wen, Dar , KUO, Chi-Hsien , ADAMCZYK, Andrew, J.
IPC: C09K13/08 , C09K13/06 , H01L21/306 , H01L21/311 , H01L21/3213
Abstract: Described herein is an etching solution suitable for the simultaneous removal of silicon and silicon-germanium from a microelectronic device, which comprises: water; an oxidizer; a buffer composition comprising an amine compound (or ammonium compound) and a polyfunctional organic acid; a water-miscible solvent; and a fluoride ion source.
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公开(公告)号:WO2019067833A3
公开(公告)日:2019-04-04
申请号:PCT/US2018/053299
申请日:2018-09-28
Applicant: VERSUM MATERIALS US, LLC
Inventor: GE, Jhih, Kuei , LEE, Yi-Chia , LIU, Wen, Dar , CHEN, Tianniu
Abstract: Described herein is an aqueous composition for treating a substrate including patterns having line-space dimensions of 50 nm or below to prevent collapse of the patters, the composition comprising: a solvent system comprising water and a water-miscible organic solvent; a surface modifier that is a reaction product between an alkylamine and an organic acid; and an optional pH adjusting agent.
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公开(公告)号:WO2019067923A3
公开(公告)日:2019-04-04
申请号:PCT/US2018/053458
申请日:2018-09-28
Applicant: VERSUM MATERIALS US, LLC
Inventor: GE, Jhih, Kuei , LEE, Yi-Chia , LIU, Wen Dar , KUO, Chi-Hsien
Abstract: Stripping solutions that may replace an etching resist ashing process are provided. The stripping solutions are useful for fabricating circuits and/or forming electrodes and/or packaging/bumping applications on semiconductor devices for semiconductor integrated circuits with good photoresist removal efficiency and with low silicon oxide etch rate and low metal etch rates. Methods for their use are similarly provided. The preferred stripping agents contain polar aprotic solvent, water, hydroxylamine, corrosion inhibitor, quaternary ammonium hydroxide and optional surfactant. Further provided are integrated circuit devices and electronic interconnect structures prepared according to these methods.
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