公开(公告)号：WO2013148915A1

公开(公告)日：2013-10-03

申请号：PCT/US2013/034218

申请日：2013-03-28

Applicant: VIOLIN MEMORY, INC.

Inventor： BENNETT, Jon, C.R. ,  BIEDERMAN, Daniel, C.

IPC: G06F12/02 ,  G06F13/14

CPC classification number: G06F3/0689 ,  G06F3/0607 ,  G06F3/0632 ,  G06F3/0652 ,  G06F3/0688 ,  G06F12/0238 ,  G06F12/121 ,  G06F2212/7208

Abstract: A memory system having a plurality of modules operated so that a group of memory modules may operation in a RAID configuration having an erase hiding property. The RAID groups are mapped to areas of memory in each of the memory modules of the RAID group. More than one RAID group may be mapped to a memory module and the erase operations of the RAID groups coordinated such that the erase operations do not overlap. This may improve the utilization of a bus over which the memory module communicates with the controller. Where a memory module is replaced by a memory module having an increased storage capacity, the additional storage capacity may be mapped to an expanded logical address space.

Abstract translation: 一种具有多个模块的存储器系统，其操作使得一组存储器模块可以在具有擦除隐藏属性的RAID配置中操作。 RAID组映射到RAID组的每个内存模块中的内存区域。 可以将多于一个的RAID组映射到存储器模块，并且RAID组的擦除操作协调使得擦除操作不重叠。 这可以提高存储器模块与控制器通信的总线的利用率。 在具有增加的存储容量的存储器模块替换存储器模块的情况下，附加存储容量可以被映射到扩展的逻辑地址空间。

公开(公告)号：WO2014110095A1

公开(公告)日：2014-07-17

申请号：PCT/US2014/010624

申请日：2014-01-08

Applicant: VIOLIN MEMORY INC.

Inventor： BENNETT, Jon, C.R.

IPC: G06F12/02 ,  G06F12/06

CPC classification number: G06F12/0246 ,  G06F12/06 ,  G06F2212/7201 ,  G06F2212/7205

Abstract: A system and method of storing data in a semiconductor-type non-volatile memory is described, where a physical storage address of data is made available to a user application such as a file system and where characteristics of the memory system that may be allocated on a physical or a logical basis to a user are separately characterizable as to performance, size, redundancy, or the like. A read request to the memory system may be serviced by accessing the physical address included in the read request rather than using a logical-to-physical address lookup in the memory system. Garbage collection operations may be performed on a virtual-physical-block basis to preserve the relationship between the physical address known to the user and the actual physical location of the data.

Abstract translation: 描述了将数据存储在半导体型非易失性存储器中的系统和方法，其中数据的物理存储地址对诸如文件系统的用户应用可用，并且可以分配在存储器系统上的特性 对用户的物理或逻辑基础可以分别表现为性能，大小，冗余等。 可以通过访问读请求中包括的物理地址而不是在存储器系统中使用逻辑到物理地址查找来对存储器系统的读请求进行服务。 可以在虚拟物理块的基础上执行垃圾收集操作，以保留用户已知的物理地址与数据的实际物理位置之间的关系。

公开(公告)号：WO2014008261A1

公开(公告)日：2014-01-09

申请号：PCT/US2013/049067

申请日：2013-07-02

Applicant: VIOLIN MEMORY, INC.

Inventor： BIEDERMAN, Daniel, C. ,  BENNETT, Jon, C.R.

IPC: G06F13/14 ,  G06F12/00

CPC classification number: G06F3/0689 ,  G06F11/108

Abstract: In a memory system where memory units may be separated from each other so as to operate substantially independently, the coordination of related memory operations between such units may be by synchronization of an epoch of time and the start of an epoch of time with a common synchronization source. The source may be distributed directly to each of the memory modules of a memory unit, or through an intermediate synchronization circuit of a memory unit that is common to the modules. Where the data is stored as a RAID stripe on a plurality of synchronized modules, the read and write or erase operations performed by the modules may be arranged such that the write operations or erase operations may not substantially affect the ability to promptly read the stored data of a RAID stripe.

Abstract translation: 在存储器单元可以彼此分离以便基本上独立地操作的存储器系统中，这些单元之间的相关存储器操作的协调可以是通过同步时间的同步和时间的开始与公共同步 资源。 源可以直接分配到存储器单元的每个存储器模块，或者通过模块共有的存储器单元的中间同步电路。 在数据作为RAID条带存储在多个同步模块上的情况下，由模块执行的读取和写入或擦除操作可以被布置为使得写入操作或擦除操作可能不会基本上影响到迅速读取存储的数据的能力 的RAID条带。

公开(公告)号：WO2013158633A1

公开(公告)日：2013-10-24

申请号：PCT/US2013/036770

申请日：2013-04-16

Applicant: VIOLIN MEMORY, INC.

Inventor： BENNETT, Jon, C.R.

IPC: G06F12/00 ,  G11C16/06

CPC classification number: G06F3/065 ,  G06F3/061 ,  G06F3/0631 ,  G06F3/0679 ,  G06F11/1456 ,  G06F11/2074 ,  G06F12/0246 ,  G06F2212/7201 ,  G06F2212/7208

Abstract: A system and method of managing the storage of data in flash memory performs snapshots of the data by maintaining the data at the epoch that the snapshot is performed in the same physical memory location. Data that is modified after the snapshot is then stored to a new physical memory location and referenced to the snapshot location. When a user read operation is performed, the data is read from the original location if the read operation is for the snapshot data. The read operation for dynamic data is performed from the original location if the data has not change since the snapshot epoch, or from the referenced data location if the data has changed since the snapshot epoch. Snapshots are released by dereferencing the original location if the data has been changed since the snapshot epoch.

Abstract translation: 管理闪速存储器中的数据的系统和方法通过在同一物理存储器位置中维护在时代执行快照的数据来执行数据的快照。 快照后修改的数据然后存储到新的物理内存位置并引用快照位置。 当执行用户读取操作时，如果读取操作用于快照数据，则从原始位置读取数据。 如果数据自快照时期以来没有变化，或者如果数据自快照时期以来发生了变化，则从原始位置执行动态数据的读取操作。 如果从快照时代以来数据已被更改，则通过取消引用原始位置来释放快照。

公开(公告)号：WO2011044515A3

公开(公告)日：2011-04-14

申请号：PCT/US2010/052074

申请日：2010-10-08

Applicant: VIOLIN MEMORY, INC. ,  BENNETT, Jon, C.R.

Inventor： BENNETT, Jon, C.R.

IPC: G06F12/16 ,  G06F13/14

Abstract: A data memory system is described, where there may be an asymmetry in the time needed to write or erase data and the time needed to read data. The data may be stored using a RAID data storage arrangement and the reading, writing and erasing operations on the modules arranged such that the erasing and writing operations may be performed without significant latency for performing a read operation. Where a failure of a memory module in the memory system occurs, methods for recovering the data of the failed module are disclosed which may selected in accordance with policies that may relate to the minimizing the possibility of irretrievable data loss, or degradation of latency performance.

公开(公告)号：WO2013155368A1

公开(公告)日：2013-10-17

申请号：PCT/US2013/036295

申请日：2013-04-12

Applicant: VIOLIN MEMORY, INC.

Inventor： BENNETT, Jon, C.R.

IPC: G06F12/00 ,  G11C16/02

CPC classification number: G06F12/0292 ,  G06F12/0246 ,  G06F12/0253 ,  G06F17/30218 ,  G06F2212/7201 ,  G06F2212/7205 ,  G06F2212/7209

Abstract: A method and system for managing a flash memory system facilitates the use of TRIM or similar operations so as to release physical memory space of logical block addresses that are declared to be deleted by a user file management system. A series of data structures accounts for the levels of indirection used to manage the correspondence between a user logical block address and the physical location of the data in the memory system and to respond to user read and write requests by efficiently determining the current status of the user logical block address in the frame of reference of the memory system and substantially decoupling the TRIM management from the garbage collection and wear leveling operations.

Abstract translation: 用于管理闪速存储器系统的方法和系统便于使用TRIM或类似操作，以便释放被用户文件管理系统声明为要删除的逻辑块地址的物理存储器空间。 一系列数据结构考虑了用于管理用户逻辑块地址和存储器系统中的数据的物理位置之间的对应关系的间接级别，并通过有效地确定用户的读取和写入请求的当前状态 在存储器系统的参考系中的用户逻辑块地址，并且将TRIM管理与垃圾收集和损耗均衡操作基本上分离。

公开(公告)号：WO2011079298A2

公开(公告)日：2011-06-30

申请号：PCT/US2010/062061

申请日：2010-12-23

Applicant: VIOLIN MEMORY, INC. ,  BENNETT, Jon, C.R.

Inventor： BENNETT, Jon, C.R.

IPC: G06F13/14

CPC classification number: G06F13/1684 ,  G06F13/14 ,  G06F13/36 ,  G11C19/00 ,  H03K19/17 ,  Y02D10/14

Abstract: An interconnection system, apparatus and method is described where the motherboard may be populated with less than all of the modules that it has been designed to accept while maintaining a configuration such that in the event of a module failure, a memory controller failure, or a combination thereof, the connectivity of the remaining modules is maintained. Where data is stored using a RAID organization of the memory on the modules, the data may be reconstructed to a spare module. The system also provides for the orderly incremental expansion of the memory by adding additional memory modules and memory controllers, while maintaining the connectivity properties.

Abstract translation: 描述了一种互连系统，设备和方法，其中主板可以填充少于所有被设计为接受的模块，同时保持配置，使得在模块故障的情况下 ，内存控制器故障或其组合，保持其余模块的连通性。 在使用模块上的存储器的RAID组织来存储数据的情况下，可以将数据重构为备用模块。 该系统还通过增加额外的内存模块和内存控制器来提供内存的有序增量扩展，同时保持连接属性。

公开(公告)号：WO2008051467A1

公开(公告)日：2008-05-02

申请号：PCT/US2007/022316

申请日：2007-10-19

Applicant: VIOLIN MEMORY INC. ,  BENNETT, Jon, C.R.

Inventor： BENNETT, Jon, C.R.

IPC: G11C7/22

CPC classification number: G11C5/06 ,  G06F13/4243 ,  H03K19/17736 ,  H03K19/17764

Abstract: An interconnection system is described where data lanes may be exchanged between lines at intervals along a transmission path so that the differential time delay between bits on a plurality of the lines is reduced when determined at a receiving location. The data lanes may be bound to the lines through the operation of a configurable switch, or by a configurable switch in conjunction with predetermined manufactured connections, or a combination of the techniques. The wiring of a connectorized node module, which may include a memory device, may be configured so that the differential time delay between pairs of input lines of a node, as measured at the output of a node, is reduced.

Abstract translation: 描述了一种互连系统，其中数据通道可以沿着传输路径间隔地在线之间交换，使得当在接收位置确定时，多条线路上的位之间的差分时间延迟减小。 数据通道可以通过可配置开关的操作或可配置开关结合预定的制造连接或这些技术的组合而被绑定到线路上。 可以配置可以包括存储器设备的连接器化节点模块的布线，使得在节点的输出处测量的节点对的输入线对之间的差分时间延迟减小。