公开(公告)号：WO2021257129A1

公开(公告)日：2021-12-23

申请号：PCT/US2021/018002

申请日：2021-02-12

Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.

Inventor： WANG, Ming ,  LI, Liang ,  WAN, Jun

IPC: G11C11/56 ,  G11C16/14 ,  G11C16/34 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/16 ,  G11C16/3445 ,  G11C16/349 ,  H01L27/11565 ,  H01L27/11582

Abstract: Apparatuses and techniques are described for performing an erase operation for a set of memory cells, where the erase operation includes an all word line erase phase to save time followed by an odd-even word line erase phase to improve data retention. A transition to the odd-even word line erase phase can be triggered when the memory cells pass a first verify test which indicates that the threshold voltages of the memory cells have decreased below a first voltage. Or, the transition can be triggered when a threshold number of erase-verify iterations have been performed. The erase operation may be completed when the memory cells pass a second verify test which indicates that the threshold voltages of the memory cells have decreased below a second voltage which is less than the first voltage.