公开(公告)号：WO2023048773A1

公开(公告)日：2023-03-30

申请号：PCT/US2022/028245

申请日：2022-05-09

Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.

Inventor： WANG, Ming ,  LI, Liang ,  YUAN, Jiahui

IPC: G11C16/10 ,  G11C16/08 ,  G11C8/14 ,  G11C16/04 ,  H01L27/11524 ,  H01L27/11582

Abstract: A memory system separately programs memory cells connected by a common word line to multiple sets of data states with the set of data states having higher threshold voltage data states being programmed before the set of data states having lower threshold voltage data states. The memory system also separately programs memory cells connected by an adjacent word line to the multiple sets of data states such that memory cells connected by the adjacent word line are programmed to higher data states after memory cells connected by the common word line are programmed to higher data states and prior to memory cells connected by the common word line are programmed to lower data states.

公开(公告)号：WO2022256050A1

公开(公告)日：2022-12-08

申请号：PCT/US2022/012213

申请日：2022-01-13

Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.

Inventor： LI, Liang ,  WANG, Ming ,  TIAN, Xuan

IPC: G11C11/56 ,  G11C16/10 ,  G11C16/34 ,  G11C14/00 ,  G11C16/12

Abstract: Apparatuses and techniques are described for detecting and compensating for a set of memory cells having a slow program speed, based on a comparison between the number of program loops used to complete programming for different data states. A program loop (PL) number is stored when programming is completed for memory cells of each assigned data state. The PL number of an nth state is then compared to the PL number of another state such as the n-1st state. If the difference between the PL numbers exceeds a threshold, the set of memory cells is considered to be slow programming and a compensation is triggered. The compensation can involve increasing the program pulse width in each remaining program pulse of the program operation. In another approach, the compensation can be triggered and subsequently deactivated in the program operation.

公开(公告)号：WO2022046218A1

公开(公告)日：2022-03-03

申请号：PCT/US2021/033714

申请日：2021-05-21

Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.

Inventor： WANG, Ming ,  LI, Liang ,  ZHANG, Peng ,  ZHANG, Yanli

IPC: G11C16/08 ,  G11C8/14 ,  H01L27/11521 ,  G11C16/04 ,  G06F3/06

Abstract: Apparatuses and techniques are described for increasing channel boosting of NAND string during programming by applying a periodic low word line bias during programming. In one aspect, a low pass voltage, VpassL, is applied to designated word lines to create periodic low points or dips in the channel boosting level. A normal pass voltage, Vpass, is applied to other unselected word lines. The low points create barriers to the movement of electrons in the channel toward the selected word line, to prevent the electrons from pulling down the voltage at the channel region which is adjacent to the selected word line. VpassL can be applied to designated word lines at the source and/or drain sides of the selected word line. A control circuit can be configured with various parameters for implementing the techniques.

公开(公告)号：WO2022191863A1

公开(公告)日：2022-09-15

申请号：PCT/US2021/033671

申请日：2021-05-21

Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.

Inventor： LI, Liang ,  WANG, Ming ,  ZHEN, Qin

IPC: G11C16/16 ,  G11C16/34 ,  G11C29/50

Abstract: An erase operation for data memory cells is integrated with a process for detecting dummy memory cells and/or select gate transistors which have an out-of-range threshold voltage. In one aspect, an erase operation is performed for the data memory cells of a block followed by a supplementary verify operation for the dummy memory cells and/or select gate transistors. In another aspect, the verify operation occurs during the erase operation and, optionally, also in a supplementary verify operation. A separate pass/fail status can be set for the erase verify of the data memory cells and the verify of the dummy memory cells and/or select gate transistors operations, where the block is assigned to a potential bad block pool or bad block pool based on a status return combination. The out-of-range dummy memory cells and/or select gate transistors can be adjusted.

公开(公告)号：WO2023014413A1

公开(公告)日：2023-02-09

申请号：PCT/US2022/027541

申请日：2022-05-04

Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.

Inventor： WANG, Ming ,  LI, Liang ,  LI, Bruce ,  LI, Will ,  WANG, Yichen

IPC: G11C16/34 ,  G11C16/24

Abstract: Apparatuses and techniques are described for programming memory cells with a reduced number of program pulses. A program operation includes a first, foggy program pass followed by a second, fine program pass. The number of program loops in the foggy program pass is minimized while providing relatively narrow Vth distributions for the foggy states. The program loops include one or more checkpoint program loops in which a program speed of the memory cells is determined through a read operation. In a next program loop, the fast-programming memory cells are inhibited from programming while the slow-programming memory cells are programmed with a reduced speed by applying a program speed-reducing bit line voltage. This brings the threshold voltage of the slow-programming memory cells into alignment with the threshold voltage of the fast-programming memory cells.

公开(公告)号：WO2021257129A1

公开(公告)日：2021-12-23

申请号：PCT/US2021/018002

申请日：2021-02-12

Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.

Inventor： WANG, Ming ,  LI, Liang ,  WAN, Jun

IPC: G11C11/56 ,  G11C16/14 ,  G11C16/34 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/16 ,  G11C16/3445 ,  G11C16/349 ,  H01L27/11565 ,  H01L27/11582

Abstract: Apparatuses and techniques are described for performing an erase operation for a set of memory cells, where the erase operation includes an all word line erase phase to save time followed by an odd-even word line erase phase to improve data retention. A transition to the odd-even word line erase phase can be triggered when the memory cells pass a first verify test which indicates that the threshold voltages of the memory cells have decreased below a first voltage. Or, the transition can be triggered when a threshold number of erase-verify iterations have been performed. The erase operation may be completed when the memory cells pass a second verify test which indicates that the threshold voltages of the memory cells have decreased below a second voltage which is less than the first voltage.

公开(公告)号：WO2021194527A1

公开(公告)日：2021-09-30

申请号：PCT/US2020/035023

申请日：2020-05-28

Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.

Inventor： LI, Liang ,  WANG, Ming

IPC: G11C16/16 ,  G11C16/34 ,  G11C11/56 ,  G06F3/0607 ,  G06F3/0611 ,  G06F3/064 ,  G06F3/0652 ,  G06F3/0688 ,  G11C16/3445

Abstract: Apparatuses and techniques are described for determining if a block of memory cells is slow-erasing during an erase operation for the block. An erase operation performs an additional verify test in a specified erase-verify iteration to check the position of the upper tail of the threshold voltage distribution of the memory cells of a block. If the upper tail is too high, this indicates a slow-erasing block, even if the erase operation is successfully completed within an allowable number of erase-verify iterations. The additional verify test can be initiated using a prefix command which is transmitted with an erase command to the memory chip. Or, it can be initiated by a device parameter on the memory chip.