公开(公告)号：WO2019071016A1

公开(公告)日：2019-04-11

申请号：PCT/US2018/054427

申请日：2018-10-04

Applicant: TEXAS INSTRUMENTS INCORPORATED ,  TEXAS INSTRUMENTS INCORPORATED

Inventor： KODURI, Sreenivasan, K.

IPC: H01L23/48

Abstract: In a semiconductor packaging structure (100), a die (102) includes a bond pad (126) and a first metal layer structure (106, 107) disposed on the die (102). The first metal layer structure (106, 107) has a first width (109, 128). In the first metal layer structure, a first metal layer (107) is electrically coupled to the bond pad (124). The semiconductor packaging structure (100) also includes a first photosensitive material (104) around sides of the first metal layer structure (106, 107), and a second metal layer structure (112, 114) disposed over the first metal layer structure (106, 107) and over a portion of the first photosensitive material (104). The second metal layer structure (112, 114) is electrically coupled to the first metal layer structure (106, 107). The second metal layer structure (112, 114) has a second width (119), which is greater than the first width (109, 128). Also, the semiconductor packaging structure (100) includes a second photosensitive material (110) around sides of the second metal layer structure (112, 114).

公开(公告)号：WO2017189657A1

公开(公告)日：2017-11-02

申请号：PCT/US2017/029527

申请日：2017-04-26

Applicant: TEXAS INSTRUMENTS INCORPORATED ,  TEXAS INSTRUMENTS INCORPORATED LIMITED

Inventor： VIJAYASANKAR, Kumaran ,  LIANG, Robert ,  KUNDURU, Jyothsna ,  EOM, Kwang, Seop

IPC: H04B1/713 ,  H04W40/10 ,  H04W52/02

Abstract: In described examples, a radio communications device (300) includes a real time clock (RTC) (304) configured to run even during sleep for receiving (from a coordinator node (CN) in an asynchronous channel hopping WPAN) an asynchronous hopping sequence (AHS) frame that includes the CN's hopping sequence. A CPU (301) implements a stored sleepy device operation in asynchronous channel hopping networks algorithm (303a). The algorithm is for: determining a time stamp for the AHS frame and the CN's initial timing position within the hopping sequence; storing the time stamp; going to sleep; and upon waking up, changing a frequency band of its receive (Rx) channel to an updated fixed channel. A data request command frame is transmitted by the device on the CN's listening channel that is calculated from the CN's hopping sequence, time stamp, CN's initial timing position and current time, and the device receives an ACK frame transmitted by the CN at the updated fixed channel of Rx operation.

Abstract translation: 在所描述的示例中，无线电通信设备（300）包括实时时钟（RTC）（304），该实时时钟（RTC）（304）甚至在休眠期间也运行以用于从协调器节点（CN） 跳频WPAN）包含CN跳频序列的异步跳频序列（AHS）帧。 CPU（301）在异步信道跳频网络算法（303a）中实施存储的休眠设备操作。 该算法用于：确定AHS帧的时间戳和跳频序列内CN的初始定时位置; 存储时间戳; 去睡觉; 并在唤醒时将其接收（Rx）频道的频带改变为更新的固定频道。 由CN的跳频序列，时间戳，CN的初始定时位置和当前时间计算的CN的监听信道上的设备发送数据请求命令帧，并且设备接收CN在更新后的固定 Rx操作的通道。

公开(公告)号：WO2023049495A1

公开(公告)日：2023-03-30

申请号：PCT/US2022/044843

申请日：2022-09-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： SUBBURAJ, Karthik ,  RAO, Sandeep

IPC: G01S13/536 ,  G01S13/58 ,  G01S7/35 ,  G01S7/40 ,  G01S13/931

Abstract: An apparatus (100) includes processor cores (130) and computer-readable mediums (150) storing machine instructions for the processor cores. When executing the machine instructions, the processor cores obtain received signals for transmitted chirps from a radar sensor circuit (110). Each transmitted chirp includes an A chirp segment, a time gap, and a B chirp segment, respectively. The processor cores sample the received signals to obtain sampled data matrices Ml (A) for the A chirp segments and M1(B) for the B chirp segments. The processor cores perform a first Fourier transform (FT) on each column of M1(A) and M1(B) to obtain velocity matrices M2(A) and M2(B), respectively. The processor cores apply a phase compensation factor to M2(B) to obtain a phase corrected velocity matrix M2(B'), and concatenate M2(A) and M2(B') to obtain an aggregate velocity matrix M2(A&B'). The processor cores perform a second FT on each row of M2(A&B') to obtain a range and velocity matrix M3(A&B').

公开(公告)号：WO2023049314A1

公开(公告)日：2023-03-30

申请号：PCT/US2022/044477

申请日：2022-09-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： NGUYEN, Hau ,  PODDAR, Anindya

IPC: H01L23/00 ,  H01L23/10 ,  H01L21/304 ,  H01L21/78 ,  H01L21/52 ,  H01L21/56 ,  H01L21/48 ,  H01L23/66

Abstract: A described example (200) includes: a MEMS component (212) on a device side surface of a first semiconductor substrate (210); a second semiconductor substrate (221) bonded to the device side surface of the first semiconductor substrate by a first seal (223) patterned to form sidewalls that surround the MEMS component; a third semiconductor substrate (231) having a second seal (229) extending from a surface and bonded to the backside surface of the first semiconductor substrate (210) by the second seal, the second seal forming sidewalls of a gap (226) beneath the MEMS component (212). A trench (227) extends through the first semiconductor substrate and at least partially surrounds the MEMS component. The third semiconductor substrate (231) is mounted on a package substrate (239). A bond wire or ribbon bond (243) couples a bond pad (245) to a conductive lead (241) on the package substrate (239); and mold compound (203) covers the MEMS component, the bond wire, and a portion of the package substrate.

公开(公告)号：WO2023034181A1

公开(公告)日：2023-03-09

申请号：PCT/US2022/041819

申请日：2022-08-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： ALLAG, Tahar ,  SCOTT, Kyl, Wayne

IPC: H02J7/00

Abstract: A method (700) includes receiving, by a first device in a stack, a command from a controller (702). The stack includes multiple devices. The method also includes dissipating, by the first device, an amount of power responsive to a difference between a longest response time for the devices to respond to the command, and a device response time for the first device to respond to the command (704).

公开(公告)号：WO2023028028A1

公开(公告)日：2023-03-02

申请号：PCT/US2022/041159

申请日：2022-08-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： KIDAMBI, Vasishta ,  PATEL, Harsh ,  SAHA, Aalok, Dyuti ,  ROY, Subrato

IPC: G01R31/3183 ,  G01R31/317

Abstract: One example includes a testing method that includes connecting a capacitor having a first capacitance to an output terminal of an integrated circuit (IC) (604). The method can also include generating pulse signal responsive to an enable signal provided at least one input terminal of the IC (606) and providing a drive signal to the output terminal to cause a linearly increasing voltage across the capacitor responsive to the pulse signal. The method can also include measuring a no-load delay. The method can also include measuring the linearly increasing voltage (610) at the output terminal responsive to the drive signal. The method can also include determining a first capacitance charge time (616) for the capacitor responsive to the linearly increasing voltage reaching a threshold and determining a second capacitance charge delay for a second capacitance (620) based on the first capacitance charge time and the no-load delay.

公开(公告)号：WO2023009718A1

公开(公告)日：2023-02-02

申请号：PCT/US2022/038667

申请日：2022-07-28

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： MONROE, Scott, Allen

IPC: G06F13/42 ,  G06F11/07

Abstract: In one example, an apparatus comprises an interface circuit configured to intermittently transmit an output serial data frame, the output serial data frame including a status phase and a data phase followed by at least one fault bit (592), wherein the at least one fault bit indicates whether a fault is detected during sending of the output serial data frame.

公开(公告)号：WO2023009386A1

公开(公告)日：2023-02-02

申请号：PCT/US2022/037958

申请日：2022-07-22

Applicant: TEXAS INSTRUMENTS INCORPORATED ,  FENG, Chen ,  LIANG, Jian ,  ZHANG, Weicheng

Inventor： FENG, Chen ,  LIANG, Jian ,  ZHANG, Weicheng

IPC: H02M1/00 ,  H02M3/158 ,  G05F1/56

Abstract: In described examples, a boost converter 400 includes an inductor 206, a voltage input 202, a current regulator 212, an intermediate node 214, a transistor 220, and a regulation circuit 424. The inductor 206 has first and second terminals. The voltage input 202 provides an input voltage, and is coupled to the first inductor 206 terminal. The current regulator 212 has current regulator 212 input and output. The current regulator 212 input is coupled to the second inductor 206 terminal. The current regulator 212 allows current to flow from the current regulator 212 input to the current regulator 212 output, and not vice versa. The intermediate node 214 provides a node voltage. The transistor 220 includes a source, a drain, and a gate. The drain is coupled to the current regulator 212 output via the intermediate node 214. The regulation circuit 424 includes a first regulation input 410 coupled to receive the input voltage, a second regulation input coupled to the intermediate node 214, and a regulation output 422 coupled to the gate.

公开(公告)号：WO2023003678A1

公开(公告)日：2023-01-26

申请号：PCT/US2022/035464

申请日：2022-06-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： AGUILAR, Alvaro ,  CUI, Yutian

IPC: H02M1/00 ,  H02M3/07 ,  H02M3/158 ,  H02M1/14

Abstract: Described embodiments include a circuit for limiting power converter output ripple (400). A first transistor (QI) has a first transistor current terminal receiving an input voltage, and a second transistor current terminal coupled to a first capacitor (CFLY1). A second transistor (Q4) has a third transistor current terminal coupled to the first capacitor, and a fourth transistor current terminal is coupled to a second capacitor (CFLY2). A third transistor (Q7) has a fifth transistor current terminal coupled to the second capacitor, and a sixth transistor terminal coupled to a filter input (LO, CO). A fourth transistor (Q2) has a seventh transistor current terminal coupled to the second transistor current terminal, and an eighth transistor current terminal coupled to the sixth transistor current terminal. A fifth transistor (Q5) has a ninth transistor current terminal coupled to the fourth transistor current terminal, and a tenth transistor current terminal coupled to the sixth transistor current terminal.

公开(公告)号：WO2023278519A1

公开(公告)日：2023-01-05

申请号：PCT/US2022/035439

申请日：2022-06-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： HERNANDEZ, David ,  PALIT, Supriyo

IPC: H04R5/04 ,  H03F1/34 ,  H03F2200/03 ,  H03F3/183 ,  H04R3/00 ,  H04R3/002

Abstract: A system (200) includes a feedforward path coupled to a signal input (202). The system (200) also includes a speaker (216) coupled to the feedforward path. The system (200) includes a back electromotive force (BEMF) extractor (226) coupled to the speaker (216), where the BEMF extractor (226) has a first input, a second input, and an output. The BEMF extractor (226) includes a first summing point (228) coupled to the first input. The BEMF extractor (226) includes a resistor amplifier (230) coupled to the second input and the first summing point (228). The BEMF extractor (226) includes a high pass filter (232) coupled to the second input and to an inductor amplifier (234). The BEMF extractor (226) also includes a low pass filter (236) coupled to the first summing point (228). The BEMF extractor (226) includes a second summing point (238) coupled to the low pass filter (236), the inductor amplifier (234), and the output.