公开(公告)号：WO1992016971A1

公开(公告)日：1992-10-01

申请号：PCT/JP1992000347

申请日：1992-03-21

Applicant: SHIBATA, Tadashi ,  OHMI, Tadahiro

IPC: H01L29/788

CPC classification number: G06F7/5013 ,  G06F7/49 ,  G06F2207/482 ,  G06F2207/4826 ,  G06N3/0635 ,  G11C11/54 ,  G11C11/5621 ,  G11C16/0408 ,  G11C27/005 ,  G11C2211/5611 ,  H01L29/7881 ,  H03K19/0944

Abstract: A semiconductor device by which a circuit having the same functions as those of the conventional circuits is realized with a very small number of elements, and complex logical functions can be designed simply, and further, its layout is also possible. A semiconductor device made up of at least one neuron MOS transistor having a gate electrode provided in a potentially floating state in a portion for isolating a source and drain region via a first insulation film, and plural control electrodes which are capacitively coupled to the floating gate electrode via a second insulation film, is characterized in that the first signal is inputted to a first control gate elctrode of the first neuron MOS transistor, the first signal is inputted to a first inverter comprising one or more stages, and the output of the first inverter is inputted to a second control gate electrode which is one of the plural control gate electrodes other than the first control gate electrode.

Abstract translation: 半导体器件使得可以生产具有与常规电路相同的功能但具有非常少量的元件的电路，并且可以简单地设计复杂的逻辑功能，并且其追踪也是可能的。 一种由至少一个神经MOS晶体管组成的半导体器件，该神经MOS晶体管具有经由第一绝缘膜在源极和漏极区域的隔离部分中处于潜在浮置状态的栅极电极，以及多个 通过第二绝缘膜电容耦合到浮栅电极的控制电极的特征在于，第一信号被输入到第一神经MOS晶体管的第一控制栅电极， 第一信号被发送到包括一个或多个级的第一反相器，并且第一反相器的输出被输入到第二控制栅极电极，该第二控制栅极电极是多个控制栅极电极之一但不同于第一栅极电极 控制。

公开(公告)号：WO1996042050A1

公开(公告)日：1996-12-27

申请号：PCT/DE1996000972

申请日：1996-06-03

Applicant: SIEMENS AKTIENGESELLSCHAFT ,  THEWES, Roland ,  PRANGE, Stefan ,  WOHLRAB, Erdmute ,  WEBER, Werner

Inventor： SIEMENS AKTIENGESELLSCHAFT

IPC: G06F07/52

CPC classification number: G06F7/53 ,  G06F2207/4826 ,  H03K5/2481 ,  H03K5/249

Abstract: The invention relates to a circuit which compares a quantity supplied by a first neuron MOS field effect transistor (M1) with a reference value provided by a reference source (R). To this end there is a current mirror (SP) facilitating a comparison between a second current (I2) supplied by a reference transistor (R) and a first current (I1) supplied by the first neuron MOS field effect transistor (M1). The assessment circuit is activated or decoupled by a first switch unit (S1) and a second switch unit (S2). This ensures that no current flows in the evaluation circuit in the inoperative position. The result of comparison is applied to an inverter stage (IS). As the inverter stage (IS) is decoupled from the evaluation circuit by the first switch unit (S1), there is never an undefined level at the inverter stage (IS). Advantage can be taken of this during data processing in subsequent stages.

Abstract translation: 本发明涉及一种电路装置，与参考可变（R）提供的第一神经元MOS场效应晶体管（M1）中的一个的大小是由参考源提供的。 为了这个目的，一个电流镜（SP）被提供，其被供给的来自参考晶体管（R）的第二电流（I 2）与所述第一神经元MOS场效应晶体管（M1）的第一电流（I1）中的一个提供的允许的比较。 通过第一开关单元（S1）和第二开关单元（S2）被激活时，所述评估电路或断开。 这确保了没有电流在评估电路流动处于静止状态。 比较结果被施加到逆变器级（IS）。 因为逆变器级（IS）通过所述第一开关单元（S1）从所述评估电路去耦，在逆变器级（IS）是从来没有在不确定电平的输出（AIS）。 这可以被用来在后续阶段进一步的数据处理来获益。

公开(公告)号：WO1997033372A1

公开(公告)日：1997-09-12

申请号：PCT/DE1997000355

申请日：1997-02-27

Applicant: SIEMENS AKTIENGESELLSCHAFT ,  WEBER, Werner ,  THEWES, Roland ,  LUCK, Andreas

Inventor： SIEMENS AKTIENGESELLSCHAFT

IPC: H03K19/0944

CPC classification number: G06F7/53 ,  G06F2207/4826 ,  H03K19/0027 ,  H03K19/0813

Abstract: The subject of the application concerns threshold logic in which a non-inverting circuit branch (S) and an inverting circuit branch (S') are connected with at least one comparative weighting circuit (BC, BS), where the non-inverting circuit branch and the inverting circuit branch preferably are constructed alike and, in each case, contain at least one neuron transistor (NT1, NT1'), and where the corresponding neuron transistor gates in the non-inverting and the inverting circuit branches are activated inversely to one another.

Abstract translation: 本申请的主题涉及一种阈值的逻辑，其中，一个非反相电路分支（S）和反相电路分支（S“）与至少一个比较点评局部电路（BC，BS）被连接时，其中该非反相电路分支和反相电路分支优选地是相同的结构，并且分别具有至少 一个神经晶体管（NT1 NT1“）和包含相应的神经晶体管栅极中的非反相和在电路分支彼此反相成反比驱动。

公开(公告)号：WO1996042051A1

公开(公告)日：1996-12-27

申请号：PCT/DE1996000973

申请日：1996-06-03

Applicant: SIEMENS AKTIENGESELLSCHAFT ,  PRANGE, Stefan

Inventor： SIEMENS AKTIENGESELLSCHAFT

IPC: G06F07/52

CPC classification number: G06F7/388 ,  G06F7/523 ,  G06F2207/4826

Abstract: A binary multiplier cell is made with the aid of two neuron MOD inverters (7, 8) which links the input values multiplier bit (a1), multiplicand bit (a2), sum bit (b) of a previous partial product and transfer bit (c) of a previous partial product to an output sum bit (11) and an output transfer bit (9). The two neuron MOS inverters (7, 8) are linked in such a way and so dimensioned that, as the output value, each neuron MOS inverter has the inverted sum bit or the inverted transfer bit of the multiplier cell. This method of producing a multiplier cell substantially reduces the number of transistors needed.

Abstract translation: 有两个神经元MOS反相器的帮助下（7,8）被实现，一个乘法器，输入值乘数位（a1）中，被乘数（A2），和位（b）一种前述部分乘积，并带有前部分积的位（C）到输出 总和是位（11）和连接的一个输出进位比特（9）。 两个神经MOS反相器（7,8）以这样的方式被连接和尺寸使得具有作为输出的每个神经元的MOS倒相器的倒总和位和乘法器的反转进位。 通过实现这样一个乘数的需要的晶体管数量大幅节省得以实现。

公开(公告)号：WO1996042049A1

公开(公告)日：1996-12-27

申请号：PCT/DE1996000971

申请日：1996-06-03

Applicant: SIEMENS AKTIENGESELLSCHAFT ,  THEWES, Roland ,  PRANGE, Stefan ,  WOHLRAB, Erdmute ,  WEBER, Werner

Inventor： SIEMENS AKTIENGESELLSCHAFT

IPC: G06F07/52

CPC classification number: G06F7/53 ,  G06F2207/4826

Abstract: The invention relates to a circuit by means of which two electrical quantities in the form of a first transverse current (I1) and a second transverse current (I2) can be mutually compared. The circuit has a first inverter stage (n1, p1). An output (50, 51) of the two inverter stages (n1, p1, n2, p2) are coupled to an input of the other inverter stage (52, 53). Between the two outputs of the two inverter stages (n1, p2) there is a reset unit (5) which, on being activated, starts the current comparison. If the reset unit (5) is deactivated, the output datum obtained during the evaluation remains stable.

Abstract translation: 本发明涉及一种电路装置，通过该两个电量与在第一交叉电流（I1）的形式彼此和第二横流（I2）进行比较。 该电路装置具有第一倒相级（N1，P1）和在第二逆变器级（N 2，P 2）。 两个逆变级（N1，P1，N2，P2）中的一个输出端（50，51）被连接到耦接的另一逆变器级（52，53）的输入。 两个逆变级（N1，P2）的两个输出端之间是启动在激活时电流的比较的复位单元（5）。 如果复位单元（5）被禁用，在评估中获得的输出数据保持稳定。