Abstract:
The invention relates to a circuit by means of which all logic elements which can be represented in the form of a threshold equation can be produced. To this end, parallel transistors (T1, T2, T3, ..., Tn) of a transistor unit are dimensioned so that the transverse currents (It1, It2, It3, ..., Itn) flowing through the transistors (T1, T2, T3, ..., Tn) represents a weighted summand of a first term of the threshold equation. A second term in the threshold equation is formed by a reference current IR representing the value of the second term. An evaluation unit (BE) compares a total current found from the sum of the transverse currents (It1, It2, It3, ..., Itn with the reference current IR. The result of evaluation is provided in the form of a stable output signal at an output of the evaluation unit (BE).
Abstract:
The invention relates to a circuit by means of which two electrical quantities in the form of a first transverse current (I1) and a second transverse current (I2) can be mutually compared. The circuit has a first inverter stage (n1, p1). An output (50, 51) of the two inverter stages (n1, p1, n2, p2) are coupled to an input of the other inverter stage (52, 53). Between the two outputs of the two inverter stages (n1, p2) there is a reset unit (5) which, on being activated, starts the current comparison. If the reset unit (5) is deactivated, the output datum obtained during the evaluation remains stable.
Abstract:
Eine Zeiterfassungsvorrichtung verwendet eine Floating-Gate-Zelle, bei der eine ON-Schichtstruktur bzw. eine ONO-Schichtstruktur zwischen Floating-Gate und Steuer-Gate vorgesehen ist. Eine Ladungsinjektionseinrichtung ist vorgesehen, um Ladungen in die Floating-Gate-Elektrode und in die Nitridschicht der ON-Struktur bzw. der ONO-Schichtstruktur zu injizieren, indem eine Spannung oder Spannungspulse an die Steuer-Gate-Elektrode angelegt werden, wobei sich ein Schwerpunkt der in die Nitridschicht injizierten Ladungen an der Grenzfläche zwischen Oxidschicht und Nitridschicht der Schichtfolge befindet. Die Zeiterfassungsvorrichtung umfaßt ferner eine Einrichtung zum Erfassen einer seit dem Injizieren der Ladungen verstrichenen Zeit basierend auf Änderungen des Übertragungsverhaltens des Kanalbereichs, die durch eine Verschiebung des Schwerpunkts der Ladungen in der Nitridschicht von der Grenzfläche weg bewirkt werden.
Abstract:
The invention relates to a time-detection device using a floating-gate-cell, wherein an ON-layer structure or a ONO-layer structure is provided between the floating-gate and the control-gate. A charge injection device is supplied in order to insert the floating-gate-electrode into the nitride layer of the ON-structure or the ONO-layer structure, wherein a voltage or a voltage pulse is applied to the control-gate-electrode, the centre of gravity of the charges injected into the nitride layer being located on the defining surface. Said time-detection device also comprises a device for detecting time elapsed since injection of the charges, based on changes in the transmission behaviour of the channel area, which are effected by displacement of the centre of gravity of the charges in the nitride layer away from the defining surface.
Abstract:
The invention relates to a circuit which compares a quantity supplied by a first neuron MOS field effect transistor (M1) with a reference value provided by a reference source (R). To this end there is a current mirror (SP) facilitating a comparison between a second current (I2) supplied by a reference transistor (R) and a first current (I1) supplied by the first neuron MOS field effect transistor (M1). The assessment circuit is activated or decoupled by a first switch unit (S1) and a second switch unit (S2). This ensures that no current flows in the evaluation circuit in the inoperative position. The result of comparison is applied to an inverter stage (IS). As the inverter stage (IS) is decoupled from the evaluation circuit by the first switch unit (S1), there is never an undefined level at the inverter stage (IS). Advantage can be taken of this during data processing in subsequent stages.